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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue50 / idct.d / cp3_test.vhd @ 2051e520

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1 2051e520 Arnaud Dieumegard
-- written by Alban Bourge @ TIMA
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.pkg_tb.all;
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entity cp3_test is
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	port(
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				clock   : in std_logic;
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				reset   : in std_logic;
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				n_error : out std_logic;
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				stopped : out std_logic
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			);
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end cp3_test;
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architecture rtl of cp3_test is
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	--TOP signals
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	signal reset_top   : std_logic := '0';
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	signal stdin_data  : stdin_vector;
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	signal stdin_rdy   : std_logic;
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	signal stdin_ack   : std_logic;
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	signal stdout_data : stdout_vector;
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	signal stdout_rdy  : std_logic;
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	signal stdout_ack  : std_logic;
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	--ASSERT_UNIT signals
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	signal context_uut : context_t;
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	signal en_feed     : std_logic;
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	signal en_check    : std_logic;
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	signal n_error_s   : std_logic;
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	signal vecs_found  : std_logic;
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	signal vec_read    : std_logic;
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	--PROG unit signals
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	signal instr_next  : instruction;
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	-- FSM unit signals
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	signal step        : std_logic;
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	signal start       : std_logic;
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	-- FSM signals
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	signal reset_fsm   : std_logic;
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	signal stopped_s   : std_logic;
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--------------------------------------
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--   PART OF ARCHITECTURE WITH CP3  --
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	--TOP signals
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	signal cp_en       : std_logic := '0';
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	signal cp_rest     : std_logic := '0';
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	signal cp_ok       : std_logic;
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	signal cp_din      : cp_vector := (others => '0');
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	signal cp_dout     : cp_vector;
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	--RAM signals
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	signal ram_1       : ram_instruction;
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	signal ram_2       : ram_instruction;
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	signal address1    : std_logic_vector(12 downto 0) := (others => '0');
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	signal address2    : std_logic_vector(12 downto 0) := (others => '0');
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	signal datain      : cp_vector := (others => '0');
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	signal dout1       : cp_vector;
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	signal dout2       : cp_vector;
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	--dut component declaration
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	component top is
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		port (
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			clock : in  std_logic;
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			reset : in  std_logic;
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			start : in  std_logic;
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			stdin_data : in  stdin_vector;
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			stdin_rdy : out std_logic;
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			stdin_ack : in  std_logic;
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			stdout_data : out stdout_vector;
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			stdout_rdy : out std_logic;
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			stdout_ack : in  std_logic;
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			cp_en : in  std_logic;
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			cp_rest : in  std_logic;
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			cp_din : in  cp_vector;
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			cp_dout : out cp_vector;
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			cp_ok : out std_logic
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		);
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	end component top;
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begin
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	uut : entity work.top(augh)
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	port map(
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						clock       => clock,
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						reset       => reset_top,
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						start       => start,
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						stdin_data  => stdin_data,
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						stdin_rdy   => stdin_rdy,
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						stdin_ack   => stdin_ack,
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						cp_en       => cp_en,
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						cp_rest     => cp_rest,
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						cp_ok       => cp_ok,
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						cp_din      => cp_din,
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						cp_dout     => cp_dout,
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						stdout_data => stdout_data,
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						stdout_rdy  => stdout_rdy,
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						stdout_ack  => stdout_ack
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					);
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	ram1 : entity work.sync_ram(rtl)
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	port map(
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						clock   => clock,
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						we      => ram_1.we,
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						address => address1,
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						datain  => datain,
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						dataout => dout1
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					);
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	ram2 : entity work.sync_ram(rtl)
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	port map(
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						clock   => clock,
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						we      => ram_2.we,
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						address => address2,
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						datain  => datain,
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						dataout => dout2
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					);
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	fsm_unit : entity work.fsm(rtl)
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	port map(
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						clock      => clock,
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						reset      => reset,
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						--prog interface
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						instr_next => instr_next,
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						step       => step,
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						--uut interface
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						cp_ok      => cp_ok,
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						stdin_rdy  => stdin_rdy,
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						stdin_ack  => stdin_ack,
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						reset_fsm  => reset_fsm,
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						start      => start,
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						cp_en      => cp_en,
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						cp_rest    => cp_rest,
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						--ram interface
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						ram_1      => ram_1,
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						ram_2      => ram_2,
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						--assert_uut interface
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						context_uut => context_uut,
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						en_feed    => en_feed,
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						en_check   => en_check,
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						vecs_found => vecs_found,
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						vec_read   => vec_read,
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						--tb interface
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						stopped    => stopped_s
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					);
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	--RAM ADDRESS controller 1
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	ram_ctrl1 : process(clock, reset)
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	begin
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		if (reset = '1') then
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			address1 <= (others => '0');
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		elsif rising_edge(clock) then
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			if (ram_1.addr_z = '1') then
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				address1 <= (others => '0');
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			elsif (ram_1.addr_up = '1') then
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				address1 <= std_logic_vector(unsigned(address1) + 1);
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			end if;
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		end if;
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	end process ram_ctrl1;
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	--RAM ADDRESS controller 2
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	ram_ctrl2 : process(clock, reset)
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	begin
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		if (reset = '1') then
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			address2 <= (others => '0');
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		elsif rising_edge(clock) then
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			if (ram_2.addr_z = '1') then
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				address2 <= (others => '0');
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			elsif (ram_2.addr_up = '1') then
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				address2 <= std_logic_vector(unsigned(address2) + 1);
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			end if;
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		end if;
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	end process ram_ctrl2;
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	--other comb signals
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	datain <= cp_dout;
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	cp_din <= dout2 when ram_2.sel = '1' else dout1;
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--   END OF ARCHITECTURE WITH CP3  --
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--------------------------------------
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--------------------------------------
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-- PART OF ARCHITECTURE WITHOUT CP3 --
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--
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--	--dut component declaration
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--	component top is
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--		port (
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--			clock : in  std_logic;
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--			reset : in  std_logic;
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--			start : in  std_logic;
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--			stdin_data : in  stdin_vector;
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--			stdin_rdy : out std_logic;
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--			stdin_ack : in  std_logic;
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--			stdout_data : out stdout_vector;
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--			stdout_rdy : out std_logic;
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--			stdout_ack : in  std_logic
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--		);
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--	end component top;
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--
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--begin
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--
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--	uut : entity work.top(augh)
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--	port map(
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--						clock       => clock,
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--						reset       => reset_top,
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--						start       => start,
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--						stdin_data  => stdin_data,
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--						stdin_rdy   => stdin_rdy,
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--						stdin_ack   => stdin_ack,
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--						stdout_data => stdout_data,
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--						stdout_rdy  => stdout_rdy,
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--						stdout_ack  => stdout_ack
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--					);
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--
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--	fsm_unit : entity work.fsm(rtl)
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--	port map(
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--						clock      => clock,
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--						reset      => reset,
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--						--prog interface
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--						instr_next => instr_next,
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--						step       => step,
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--						--uut interface
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--						cp_ok      => '0',
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--						stdin_rdy  => stdin_rdy,
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--						stdin_ack  => stdin_ack,
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--						reset_fsm  => reset_fsm,
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--						start      => start,
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--						cp_en      => open,
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--						cp_rest    => open,
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--						--ram interface
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--						ram_1      => open,
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--						ram_2      => open,
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--						--assert_uut interface
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--						context_uut => context_uut,
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--						en_feed    => en_feed,
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--						en_check   => en_check,
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--						vecs_found => vecs_found,
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--						vec_read   => vec_read,
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--						--tb interface
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--						stopped    => stopped_s
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--					);
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--
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-- END OF ARCHITECTURE WITHOUT CP3 --
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--------------------------------------
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	assert_unit : entity work.assert_uut(rtl)
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	port map(
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						clock       => clock,
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						reset       => reset,
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						context_uut => context_uut,
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						en_feed     => en_feed,
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						stdin_rdy   => stdin_rdy,
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						stdin_ack   => stdin_ack,
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						stdin_data  => stdin_data,
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						en_check    => en_check,
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						stdout_rdy  => stdout_rdy,
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						stdout_ack  => stdout_ack,
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						stdout_data => stdout_data,
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						vecs_found  => vecs_found,
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						vec_read    => vec_read,
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						n_error     => n_error_s
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					);
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	prog_unit : entity work.prog(rtl)
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	port map(
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						clock      => clock,
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						reset      => reset,
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						step       => step,
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						instr_next => instr_next
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					);
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	--other comb signals
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	reset_top <= reset or reset_fsm;
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	--outputs
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	n_error <= n_error_s;
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	stopped <= stopped_s;
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end rtl;