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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue382 / demo.vhd @ 2051e520

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1 2051e520 Arnaud Dieumegard
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity demo is
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        port (
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                clk,reset: in std_logic;
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                load:   in std_logic;
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                load_val: in unsigned(7 downto 0);
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                qout: out unsigned(7 downto 0);
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                is5: out std_logic
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                );
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end entity;
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architecture v1 of demo is
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        signal q: unsigned(7 downto 0); 
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begin
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        qout<=q;
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--        is5<='1' when q=x"05" else '0';
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        process(clk, reset)
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        begin
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                if reset='1' then
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                        q<=(others=>'0');
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                        is5<='0';
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                elsif rising_edge(clk) then
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                        is5<='0';
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                        if q=x"04" then
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                                is5<='1';
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                        end if;
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                        if load='1' then
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                                q<=load_val;
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                                if load_val=x"05" then
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                                        is5<='1';
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                                end if;
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                        else
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                                q<=q+1;
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                        end if;
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                end if;
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        end process;
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end v1;