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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue301 / src / axi4s_buffer.vhd @ 2051e520

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1 2051e520 Arnaud Dieumegard
--!
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--! Copyright (C) 2012 - 2014 Creonic GmbH
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--!
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--! This file is part of the Creonic Viterbi Decoder, which is distributed
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--! under the terms of the GNU General Public License version 2.
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--!
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--! @file
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--! @brief  AXI4-Stream buffer that allows to buffer the accept-signal.
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--! @author Matthias Alles
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--! @date   2012/04/18
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--!
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--! @details
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--! One problem when concatenating multiple AXI4-Stream builind blocks is that
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--! the accept signal has to pass from the very last component to the input
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--! of the very first component. Only then it is possible to have an interruption
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--! free data processing within the whole chain. The drawback of this approach is
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--! that the accept signal has a long path and high fanouts.
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--! This entity allows to use registers on the accept signals by introducing buffers
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--! for storing the input values. It should improve timing of bigger building blocks.
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--!
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library ieee;
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use ieee.std_logic_1164.all;
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entity axi4s_buffer is
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	generic (
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		DATA_WIDTH : natural := 1
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	);
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	port (
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	clk            : in  std_logic;
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	rst            : in  std_logic;
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	-- Input data handling
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	----------------------
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	input          : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
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	input_valid    : in  std_logic;
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	input_last     : in  std_logic;
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	input_accept   : out std_logic;
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	-- Output data handling
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	-----------------------
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	output         : out std_logic_vector(DATA_WIDTH - 1 downto 0);
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	output_valid   : out std_logic;
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	output_last    : out std_logic;
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	output_accept  : in  std_logic
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);
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end entity axi4s_buffer;
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architecture rtl of axi4s_buffer is
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	signal input_accept_int : std_logic;
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	signal output_reg        : std_logic_vector(DATA_WIDTH - 1 downto 0);
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	signal output_last_reg   : std_logic;
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	signal output_valid_reg  : std_logic;
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	signal buffer_full : std_logic;
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	signal buffer_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
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	signal buffer_last : std_logic;
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begin
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	input_accept <= input_accept_int;
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	output       <= output_reg;
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	output_last  <= output_last_reg;
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	output_valid <= output_valid_reg;
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	--
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	-- This process registers all signals.
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	-- No combinatorial logic is bypassed from input to output and vice versa.
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	--
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	pr_reg: process(clk) is
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	begin
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	if rising_edge(clk) then
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		if rst = '1' then
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			output_reg        <= (others => '0');
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			output_last_reg   <= '0';
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			output_valid_reg  <= '0';
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			input_accept_int <= '1';
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			buffer_full <= '0';
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			buffer_data <= (others => '0');
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			buffer_last <= '0';
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		else
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			--
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			-- Data is coming, buf output data can't be sent => Store input data in buffer
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			-- and remove input_accept signal!
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			--
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			if input_valid = '1' and input_accept_int = '1' and output_valid_reg = '1' and output_accept = '0' then
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				buffer_data      <= input;
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				buffer_last      <= input_last;
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				buffer_full      <= '1';
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				input_accept_int <= '0';
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			end if;
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			--
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			-- Output data is being read but there is data in the buffer waiting for being sent
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			-- => Use the buffer data!
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			--
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			if output_accept = '1' and output_valid_reg = '1' and buffer_full = '1' then
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				output_reg       <= buffer_data;
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				output_last_reg  <= buffer_last;
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				output_valid_reg <= '1';
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				buffer_full      <= '0';
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				input_accept_int <= '1';
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			--
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			-- Data is being read and buffer is empty => Use input data directly!
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			-- Output register is empty => Use input data directly!
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			--
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			elsif (output_accept = '1' and output_valid_reg = '1') or output_valid_reg = '0' then
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				output_reg       <= input;
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				output_last_reg  <= input_last;
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				output_valid_reg <= input_valid;
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			end if;
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		end if;
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	end if;
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	end process pr_reg;
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end architecture rtl;