## lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / issue301 / packages / pkg_components.vhd @ 2051e520

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1 | 2051e520 | Arnaud Dieumegard | --! |
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2 | --! Copyright (C) 2011 - 2014 Creonic GmbH |
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3 | --! |
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4 | --! This file is part of the Creonic Viterbi Decoder, which is distributed |
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5 | --! under the terms of the GNU General Public License version 2. |
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6 | --! |
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7 | --! @file |
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8 | --! @brief Component declarations for Viterbi decoder |
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9 | --! @author Markus Fehrenz |
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10 | --! @date 2011/04/07 |
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11 | --! |
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12 | --! |
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13 | |||

14 | library ieee; |
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15 | use ieee.std_logic_1164.all; |
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16 | use ieee.numeric_std.all; |
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17 | |||

18 | library dec_viterbi; |
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19 | use dec_viterbi.pkg_param.all; |
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20 | use dec_viterbi.pkg_param_derived.all; |
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21 | use dec_viterbi.pkg_types.all; |
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22 | |||

23 | package pkg_components is |
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24 | |||

25 | component axi4s_buffer is |
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26 | generic ( |
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27 | DATA_WIDTH : natural := 1 |
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28 | ); |
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29 | port ( |
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30 | clk : in std_logic; |
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31 | rst : in std_logic; |
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32 | |||

33 | input : in std_logic_vector(DATA_WIDTH - 1 downto 0); |
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34 | input_valid : in std_logic; |
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35 | input_last : in std_logic; |
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36 | input_accept : out std_logic; |
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37 | |||

38 | output : out std_logic_vector(DATA_WIDTH - 1 downto 0); |
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39 | output_valid : out std_logic; |
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40 | output_last : out std_logic; |
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41 | output_accept : in std_logic |
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42 | ); |
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43 | end component axi4s_buffer; |
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44 | |||

45 | component branch_distance is |
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46 | generic( |
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47 | EDGE_WEIGHT : in std_logic_vector(NUMBER_PARITY_BITS - 1 downto 0) |
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48 | ); |
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49 | port( |
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50 | clk : in std_logic; |
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51 | rst : in std_logic; |
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52 | |||

53 | s_axis_input_tvalid : in std_logic; |
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54 | s_axis_input_tdata : in t_input_block; |
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55 | s_axis_input_tlast : in std_logic; |
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56 | s_axis_input_tready : out std_logic; |
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57 | |||

58 | m_axis_output_tvalid : out std_logic; |
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59 | m_axis_output_tdata : out std_logic_vector(BW_BRANCH_RESULT - 1 downto 0); |
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60 | m_axis_output_tlast : out std_logic; |
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61 | m_axis_output_tready : in std_logic |
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62 | |||

63 | ); |
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64 | end component branch_distance; |
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65 | |||

66 | component acs is |
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67 | generic( |
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68 | initialize_value : in signed(BW_MAX_PROBABILITY - 1 downto 0) |
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69 | ); |
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70 | port( |
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71 | clk : in std_logic; |
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72 | rst : in std_logic; |
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73 | |||

74 | s_axis_inbranch_tvalid : in std_logic; |
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75 | s_axis_inbranch_tdata_low : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0); |
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76 | s_axis_inbranch_tdata_high : in std_logic_vector(BW_BRANCH_RESULT - 1 downto 0); |
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77 | s_axis_inbranch_tlast : in std_logic; |
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78 | s_axis_inbranch_tready : out std_logic; |
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79 | |||

80 | s_axis_inprev_tvalid : in std_logic; |
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81 | s_axis_inprev_tdata_low : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0); |
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82 | s_axis_inprev_tdata_high : in std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0); |
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83 | s_axis_inprev_tready : out std_logic; |
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84 | |||

85 | m_axis_outprob_tvalid : out std_logic; |
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86 | m_axis_outprob_tdata : out std_logic_vector(BW_MAX_PROBABILITY - 1 downto 0); |
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87 | m_axis_outprob_tready : in std_logic; |
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88 | |||

89 | m_axis_outdec_tvalid : out std_logic; |
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90 | m_axis_outdec_tdata : out std_logic; |
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91 | m_axis_outdec_tlast : out std_logic; |
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92 | m_axis_outdec_tready : in std_logic |
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93 | ); |
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94 | end component acs; |
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95 | |||

96 | component ram_ctrl is |
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97 | port( |
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98 | clk : in std_logic; |
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99 | rst : in std_logic; |
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100 | |||

101 | s_axis_input_tvalid : in std_logic; |
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102 | s_axis_input_tdata : in std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0); |
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103 | s_axis_input_tlast : in std_logic; |
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104 | s_axis_input_tready : out std_logic; |
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105 | |||

106 | m_axis_output_tvalid : out std_logic_vector(1 downto 0); |
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107 | m_axis_output_tdata : out t_ram_rd_data; |
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108 | m_axis_output_tlast : out std_logic_vector(1 downto 0); |
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109 | m_axis_output_tready : in std_logic_vector(1 downto 0); |
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110 | m_axis_output_window_tuser : out std_logic_vector(1 downto 0); |
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111 | m_axis_output_last_tuser : out std_logic_vector(1 downto 0); |
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112 | |||

113 | s_axis_ctrl_tvalid : in std_logic; |
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114 | s_axis_ctrl_tdata : in std_logic_vector(31 downto 0); |
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115 | s_axis_ctrl_tready : out std_logic |
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116 | ); |
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117 | end component ram_ctrl; |
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118 | |||

119 | component generic_sp_ram is |
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120 | generic( |
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121 | DISTR_RAM : boolean; |
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122 | WORDS : integer; |
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123 | BITWIDTH : integer |
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124 | ); |
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125 | port( |
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126 | clk : in std_logic; |
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127 | rst : in std_logic; |
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128 | |||

129 | wen : in std_logic; |
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130 | en : in std_logic; |
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131 | |||

132 | a : in std_logic_vector(BW_MAX_WINDOW_LENGTH - 1 downto 0); |
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133 | d : in std_logic_vector(BITWIDTH - 1 downto 0 ); |
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134 | q : out std_logic_vector(BITWIDTH - 1 downto 0) |
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135 | ); |
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136 | end component generic_sp_ram; |
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137 | |||

138 | component trellis_traceback is |
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139 | port( |
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140 | clk : in std_logic; |
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141 | rst : in std_logic; |
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142 | |||

143 | s_axis_input_tvalid : in std_logic; |
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144 | s_axis_input_tdata : in std_logic_vector(NUMBER_TRELLIS_STATES - 1 downto 0); |
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145 | s_axis_input_tlast : in std_logic; |
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146 | s_axis_input_tready : out std_logic; |
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147 | s_axis_input_window_tuser : in std_logic; |
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148 | s_axis_input_last_tuser : in std_logic; |
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149 | |||

150 | m_axis_output_tvalid : out std_logic; |
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151 | m_axis_output_tdata : out std_logic; |
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152 | m_axis_output_tlast : out std_logic; |
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153 | m_axis_output_last_tuser : out std_logic; |
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154 | m_axis_output_tready : in std_logic |
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155 | ); |
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156 | end component trellis_traceback; |
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157 | |||

158 | component reorder is |
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159 | port( |
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160 | clk : in std_logic; |
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161 | rst : in std_logic; |
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162 | |||

163 | s_axis_input_tvalid : in std_logic; |
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164 | s_axis_input_tdata : in std_logic; |
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165 | s_axis_input_tlast : in std_logic; |
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166 | s_axis_input_last_tuser : in std_logic; |
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167 | s_axis_input_tready : out std_logic; |
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168 | |||

169 | m_axis_output_tvalid : out std_logic; |
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170 | m_axis_output_tdata : out std_logic; |
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171 | m_axis_output_tlast : out std_logic; |
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172 | m_axis_output_last_tuser : out std_logic; |
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173 | m_axis_output_tready : in std_logic |
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174 | ); |
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175 | end component reorder; |
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176 | |||

177 | component recursionx is |
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178 | port( |
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179 | clk : in std_logic; |
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180 | rst : in std_logic; |
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181 | |||

182 | s_axis_input_tvalid : in std_logic; |
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183 | s_axis_input_tdata : in std_logic; |
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184 | s_axis_input_tlast : in std_logic; |
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185 | s_axis_input_tready : out std_logic; |
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186 | |||

187 | m_axis_output_tvalid : out std_logic; |
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188 | m_axis_output_tdata : out std_logic; |
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189 | m_axis_output_tlast : out std_logic; |
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190 | m_axis_output_tready : in std_logic |
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191 | ); |
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192 | end component recursionx; |
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193 | |||

194 | end package pkg_components; |