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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / bug16695 / lfsr_updown_tb.vhd @ 2051e520

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1 2051e520 Arnaud Dieumegard
-------------------------------------------------------
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-- Design Name : lfsr
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-- File Name   : lfsr_updown_tb.vhd
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-- Function    : Linear feedback shift register
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-- Coder       : Deepak Kumar Tala (Verilog)
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-- Translator  : Alexander H Pham (VHDL)
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-------------------------------------------------------
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library ieee;
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    use ieee.std_logic_1164.all;
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    use ieee.std_logic_textio.all;
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    use std.textio.all;
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entity lfsr_updown_tb is
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end entity;
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architecture test of lfsr_updown_tb is
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    constant WIDTH :integer := 8;
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    signal clk       :std_logic := '0';
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    signal reset     :std_logic := '1';
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    signal enable    :std_logic := '0';
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    signal up_down   :std_logic := '0';
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    signal count     :std_logic_vector (WIDTH-1 downto 0);
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    signal overflow  :std_logic;
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    component lfsr_updown is
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    generic (
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        WIDTH :integer := 8
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    );
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    port (
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        clk       :in  std_logic;                       -- Clock input
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        reset     :in  std_logic;                       -- Reset input
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        enable    :in  std_logic;                       -- Enable input
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        up_down   :in  std_logic;                       -- Up Down input
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        count     :out std_logic_vector (WIDTH-1 downto 0);   -- Count output
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        overflow  :out std_logic                        -- Overflow output
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    );
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    end component;
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    constant PERIOD :time := 20 ns;
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begin
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    clk     <= not clk after PERIOD/2;
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    reset   <= '0' after PERIOD*10;
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    enable  <= '1' after PERIOD*11;
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    up_down <= '1' after PERIOD*22;
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    -- Display the time and result
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    process (reset, enable, up_down, count, overflow)
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        variable wrbuf :line;
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    begin
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        write(wrbuf, string'("Time: "     )); 
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        writeline(output, wrbuf);
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	write(wrbuf, now);
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        writeline(output, wrbuf);
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        write(wrbuf, string'(" rst: "     )); 
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        writeline(output, wrbuf);
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	write(wrbuf, reset);
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        writeline(output, wrbuf);
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        write(wrbuf, string'(" enable: "  )); 
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        writeline(output, wrbuf);
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	write(wrbuf, enable);
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        writeline(output, wrbuf);
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        write(wrbuf, string'(" up_down: " )); 
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        writeline(output, wrbuf);
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	write(wrbuf, up_down);
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        writeline(output, wrbuf);
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        write(wrbuf, string'(" count: "   )); 
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        writeline(output, wrbuf);
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	write(wrbuf, count);
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        writeline(output, wrbuf);
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        write(wrbuf, string'(" overflow: ")); 
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        writeline(output, wrbuf);
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	write(wrbuf, overflow);
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        writeline(output, wrbuf);
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    end process;
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    Inst_lfsr_updown : lfsr_updown
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    port map (
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        clk      => clk,
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        reset    => reset,
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        enable   => enable,
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        up_down  => up_down,
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        count    => count,
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        overflow => overflow
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    );
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end architecture;