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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / bug040 / zigzag_index.vhd @ 2051e520

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1 2051e520 Arnaud Dieumegard
library ieee;
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use ieee.std_logic_1164.all;
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library ieee;
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use ieee.numeric_std.all;
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entity zigzag_index is
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	port (
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		clk : in  std_logic;
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		ra0_addr : in  std_logic_vector(5 downto 0);
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		ra0_data : out std_logic_vector(5 downto 0)
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	);
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end zigzag_index;
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architecture augh of zigzag_index is
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	-- Embedded RAM
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	type ram_type is array (0 to 63) of std_logic_vector(5 downto 0);
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	signal ram : ram_type := (
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		"000000", "000001", "000101", "000110", "001110", "001111", "011011", "011100", "000010", "000100", "000111", "001101",
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		"010000", "011010", "011101", "101010", "000011", "001000", "001100", "010001", "011001", "011110", "101001", "101011",
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		"001001", "001011", "010010", "011000", "011111", "101000", "101100", "110101", "001010", "010011", "010111", "100000",
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		"100111", "101101", "110100", "110110", "010100", "010110", "100001", "100110", "101110", "110011", "110111", "111100",
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		"010101", "100010", "100101", "101111", "110010", "111000", "111011", "111101", "100011", "100100", "110000", "110001",
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		"111001", "111010", "111110", "111111"
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	);
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	-- Little utility functions to make VHDL syntactically correct
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	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
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	--   This happens when accessing arrays with <= 2 cells, for example.
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	function to_integer(B: std_logic) return integer is
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		variable V: std_logic_vector(0 to 0);
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	begin
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		V(0) := B;
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		return to_integer(unsigned(V));
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	end;
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	function to_integer(V: std_logic_vector) return integer is
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	begin
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		return to_integer(unsigned(V));
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	end;
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begin
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	-- The component is a ROM.
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	-- There is no Write side.
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	-- The Read side (the outputs)
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	ra0_data <= ram( to_integer(ra0_addr) );
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end architecture;