lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / bug040 / sub_206.vhd @ 2051e520
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1 | 2051e520 | Arnaud Dieumegard | library ieee; |
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2 | use ieee.std_logic_1164.all; |
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3 | |||
4 | library ieee; |
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5 | use ieee.numeric_std.all; |
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6 | |||
7 | entity sub_206 is |
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8 | port ( |
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9 | gt : out std_logic; |
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10 | output : out std_logic_vector(40 downto 0); |
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11 | sign : in std_logic; |
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12 | in_b : in std_logic_vector(40 downto 0); |
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13 | in_a : in std_logic_vector(40 downto 0) |
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14 | ); |
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15 | end sub_206; |
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16 | |||
17 | architecture augh of sub_206 is |
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18 | |||
19 | signal carry_inA : std_logic_vector(42 downto 0); |
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20 | signal carry_inB : std_logic_vector(42 downto 0); |
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21 | signal carry_res : std_logic_vector(42 downto 0); |
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22 | |||
23 | -- Signals to generate the comparison outputs |
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24 | signal msb_abr : std_logic_vector(2 downto 0); |
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25 | signal tmp_sign : std_logic; |
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26 | signal tmp_eq : std_logic; |
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27 | signal tmp_le : std_logic; |
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28 | signal tmp_ge : std_logic; |
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29 | |||
30 | begin |
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31 | |||
32 | -- To handle the CI input, the operation is '0' - CI |
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33 | -- If CI is not present, the operation is '0' - '0' |
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34 | carry_inA <= '0' & in_a & '0'; |
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35 | carry_inB <= '0' & in_b & '0'; |
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36 | -- Compute the result |
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37 | carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); |
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38 | |||
39 | -- Set the outputs |
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40 | output <= carry_res(41 downto 1); |
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41 | |||
42 | -- Other comparison outputs |
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43 | |||
44 | -- Temporary signals |
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45 | msb_abr <= in_a(40) & in_b(40) & carry_res(41); |
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46 | tmp_sign <= sign; |
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47 | tmp_eq <= '1' when in_a = in_b else '0'; |
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48 | |||
49 | tmp_le <= |
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50 | tmp_eq when msb_abr = "000" or msb_abr = "110" else |
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51 | '1' when msb_abr = "001" or msb_abr = "111" else |
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52 | '1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else |
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53 | '1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else |
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54 | '0'; |
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55 | |||
56 | tmp_ge <= |
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57 | '1' when msb_abr = "000" or msb_abr = "110" else |
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58 | '1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else |
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59 | '1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else |
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60 | '0'; |
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61 | |||
62 | gt <= not(tmp_le); |
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63 | |||
64 | end architecture; |