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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / bug040 / extend_mask.vhd @ 2051e520

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1 2051e520 Arnaud Dieumegard
library ieee;
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use ieee.std_logic_1164.all;
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library ieee;
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use ieee.numeric_std.all;
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entity extend_mask is
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	port (
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		clk : in  std_logic;
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		ra0_addr : in  std_logic_vector(4 downto 0);
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		ra0_data : out std_logic_vector(20 downto 0)
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	);
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end extend_mask;
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architecture augh of extend_mask is
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	-- Embedded RAM
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	type ram_type is array (0 to 19) of std_logic_vector(20 downto 0);
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	signal ram : ram_type := (
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		"111111111111111111110", "111111111111111111100", "111111111111111111000", "111111111111111110000",
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		"111111111111111100000", "111111111111111000000", "111111111111110000000", "111111111111100000000",
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		"111111111111000000000", "111111111110000000000", "111111111100000000000", "111111111000000000000",
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		"111111110000000000000", "111111100000000000000", "111111000000000000000", "111110000000000000000",
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		"111100000000000000000", "111000000000000000000", "110000000000000000000", "100000000000000000000"
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	);
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	-- Little utility functions to make VHDL syntactically correct
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	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
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	--   This happens when accessing arrays with <= 2 cells, for example.
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	function to_integer(B: std_logic) return integer is
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		variable V: std_logic_vector(0 to 0);
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	begin
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		V(0) := B;
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		return to_integer(unsigned(V));
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	end;
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	function to_integer(V: std_logic_vector) return integer is
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	begin
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		return to_integer(unsigned(V));
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	end;
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begin
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	-- The component is a ROM.
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	-- There is no Write side.
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	-- The Read side (the outputs)
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	ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 20 else (others => '-');
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end architecture;