## lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / ghdl / ghdl / testsuite / gna / bug040 / add_202.vhd @ 2051e520

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1 | 2051e520 | Arnaud Dieumegard | library ieee; |
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2 | use ieee.std_logic_1164.all; |
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3 | |||

4 | library ieee; |
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5 | use ieee.numeric_std.all; |
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6 | |||

7 | entity add_202 is |
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8 | port ( |
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9 | output : out std_logic_vector(31 downto 0); |
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10 | in_b : in std_logic_vector(31 downto 0); |
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11 | in_a : in std_logic_vector(31 downto 0) |
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12 | ); |
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13 | end add_202; |
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14 | |||

15 | architecture augh of add_202 is |
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16 | |||

17 | signal carry_inA : std_logic_vector(33 downto 0); |
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18 | signal carry_inB : std_logic_vector(33 downto 0); |
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19 | signal carry_res : std_logic_vector(33 downto 0); |
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20 | |||

21 | begin |
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22 | |||

23 | -- To handle the CI input, the operation is '1' + CI |
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24 | -- If CI is not present, the operation is '1' + '0' |
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25 | carry_inA <= '0' & in_a & '1'; |
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26 | carry_inB <= '0' & in_b & '0'; |
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27 | -- Compute the result |
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28 | carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); |
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29 | |||

30 | -- Set the outputs |
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31 | output <= carry_res(32 downto 1); |
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32 | |||

33 | end architecture; |