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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / testcases / latches.vhd @ 2051e520

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1 2051e520 Arnaud Dieumegard
library IEEE;
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use IEEE.std_logic_1164.ALL;
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entity latches is
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   port
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   (
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      i_clock: in std_logic;
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      i_reset: in std_logic;
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      i_a:     in std_logic;
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      i_b:     in std_logic;
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      i_c:     in std_logic;
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      o_a:     out std_logic;
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      o_b:     out std_logic;
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      o_c:     out std_logic
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   );
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end entity latches;
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architecture Behavioral of latches is
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   signal latch_0: std_logic;
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begin
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   -- Taken from Xilinx's documentation:
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   -- "Latch With Positive Gate and Asynchronous Reset VHDL Coding Example"
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   -- 'latch_0' undefined for ((i_reset = '0') and (i_b = '0')), requiring the
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   -- use of memory (hence the latch).
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   process (i_reset, i_a, i_b)
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   begin
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      if (i_reset = '1')
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      then
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         latch_0 <= '0';
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      elsif (i_b = '1')
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      then
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         latch_0 <= i_a;
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      end if;
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   end process;
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end architecture;