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lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / STD_04500_good.json @ 2051e520

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1 2051e520 Arnaud Dieumegard
{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "IEEE"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "IEEE"], ["SIMPLE_NAME", "std_logic_1164"]]]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "IEEE"], ["SIMPLE_NAME", "numeric_std"]]]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["SIMPLE_NAME", "pkg_HBK"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "STD_04500_good"], "ports" : [{
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          "names" : [["IDENTIFIER", "i_Clock"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "i_Reset_n"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "i_DA"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "o_QA"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "o_QB"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "o_QC"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "Behavioral"], "entity" : ["IDENTIFIER", "STD_04500_good"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "QA"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic"]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "QB"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic"]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "DFF1"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "i_Clock"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "i_D"], "actual_designator" : ["SIMPLE_NAME", "i_DA"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "o_Q"], "actual_designator" : ["SIMPLE_NAME", "QA"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "o_Q_n"], "actual_designator" : ["SIMPLE_NAME", "open"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "DFF2"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "i_Clock"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "i_D"], "actual_designator" : ["SIMPLE_NAME", "QA"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "o_Q"], "actual_designator" : ["SIMPLE_NAME", "QB"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "o_Q_n"], "actual_designator" : ["SIMPLE_NAME", "open"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "DFF3"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "i_Clock"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "i_D"], "actual_designator" : ["SIMPLE_NAME", "QB"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "o_Q"], "actual_designator" : ["SIMPLE_NAME", "o_QC"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "o_Q_n"], "actual_designator" : ["SIMPLE_NAME", "open"]}
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          ]}
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        ], ["CONDITIONAL_SIGNAL_ASSIGNMENT", {
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          "postponed" : false, "lhs" : ["SIMPLE_NAME", "o_QA"], "rhs" : [{
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            "expr" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CALL", ["SIMPLE_NAME", "QA"]]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ]}
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        ], ["CONDITIONAL_SIGNAL_ASSIGNMENT", {
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          "postponed" : false, "lhs" : ["SIMPLE_NAME", "o_QB"], "rhs" : [{
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            "expr" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CALL", ["SIMPLE_NAME", "QB"]]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ]}
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        ]]}
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      ]}
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    ]}
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  }