lustrec-tests / vhdl_json / vhdl_files / 2-exportOK / cnes_guidelines / rule / data / CNE_04500_good.vhd @ 2051e520
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1 | 2051e520 | Arnaud Dieumegard | ------------------------------------------------------------------------------------------------- |
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2 | -- Company : CNES |
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3 | -- Author : Mickael Carl (CNES) |
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4 | -- Copyright : Copyright (c) CNES. |
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5 | -- Licensing : GNU GPLv3 |
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6 | ------------------------------------------------------------------------------------------------- |
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7 | -- Version : V1 |
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8 | -- Version history : |
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9 | -- V1 : 2015-04-17 : Mickael Carl (CNES): Creation |
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10 | ------------------------------------------------------------------------------------------------- |
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11 | -- File name : CNE_04900_good.vhd |
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12 | -- File Creation date : 2015-04-17 |
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13 | -- Project name : VHDL Handbook CNES Edition |
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14 | ------------------------------------------------------------------------------------------------- |
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15 | -- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor) |
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16 | ------------------------------------------------------------------------------------------------- |
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17 | -- Description : Handbook example: Reset registers: good example |
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18 | -- |
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19 | -- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at |
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20 | -- demonstrating good practices in VHDL and as such, its design is minimalistic. |
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21 | -- It is provided as is, without any warranty. |
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22 | -- This example is compliant with the Handbook version 1. |
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23 | -- |
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24 | ------------------------------------------------------------------------------------------------- |
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25 | -- Naming conventions: |
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26 | -- |
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27 | -- i_Port: Input entity port |
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28 | -- o_Port: Output entity port |
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29 | -- b_Port: Bidirectional entity port |
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30 | -- g_My_Generic: Generic entity port |
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31 | -- |
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32 | -- c_My_Constant: Constant definition |
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33 | -- t_My_Type: Custom type definition |
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34 | -- |
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35 | -- My_Signal_n: Active low signal |
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36 | -- v_My_Variable: Variable |
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37 | -- sm_My_Signal: FSM signal |
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38 | -- pkg_Param: Element Param coming from a package |
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39 | -- |
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40 | -- My_Signal_re: Rising edge detection of My_Signal |
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41 | -- My_Signal_fe: Falling edge detection of My_Signal |
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42 | -- My_Signal_rX: X times registered My_Signal signal |
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43 | -- |
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44 | -- P_Process_Name: Process |
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45 | -- |
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46 | ------------------------------------------------------------------------------------------------- |
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47 | |||
48 | library IEEE; |
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49 | use IEEE.std_logic_1164.all; |
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50 | use IEEE.numeric_std.all; |
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51 | |||
52 | --CODE |
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53 | entity CNE_04500_good is |
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54 | generic ( |
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55 | g_Width : positive := 4 |
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56 | ); |
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57 | port ( |
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58 | i_Clock : in std_logic; |
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59 | i_Reset_n : in std_logic; |
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60 | i_Data : in std_logic_vector(g_Width-1 downto 0); |
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61 | o_Sum : out std_logic_vector(g_Width downto 0) |
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62 | ); |
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63 | end CNE_04500_good; |
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64 | |||
65 | architecture Behavioral of CNE_04500_good is |
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66 | type Data_4_Reg is array (0 to 3) of std_logic_vector(g_Width-1 downto 0); |
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67 | signal Data_Reg : Data_4_Reg; |
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68 | signal Sum : std_logic_vector(g_Width downto 0); |
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69 | signal Sum_r : std_logic_vector(g_Width downto 0); |
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70 | begin |
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71 | p_Reg:process(i_Reset_n,i_Clock) |
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72 | begin |
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73 | if (i_Reset_n='0') then |
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74 | Data_Reg <= (others => (others => '0')); |
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75 | elsif (rising_edge(i_Clock)) then |
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76 | Data_Reg(3) <= Data_Reg(2); |
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77 | Data_Reg(2) <= Data_Reg(1); |
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78 | Data_Reg(1) <= Data_Reg(0); |
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79 | Data_Reg(0) <= i_Data; |
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80 | end if; |
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81 | end process; |
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82 | |||
83 | Sum <= std_logic_vector(unsigned('0' & Data_Reg(3)) + unsigned('0' & Data_Reg(2))); |
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84 | |||
85 | p_Reg_Uninitialized:process(i_Reset_n,i_Clock) |
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86 | begin |
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87 | if (i_Reset_n='0') then |
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88 | Sum_r <= (others => '0'); |
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89 | elsif (rising_edge(i_Clock)) then |
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90 | Sum_r <= Sum; |
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91 | end if; |
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92 | end process; |
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93 | |||
94 | o_Sum <= Sum_r; |
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95 | end Behavioral; |
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96 | --CODE |