Project

General

Profile

Revision 1a2296da vhdl_json/vhdl_files/2-exportOK/valencia/d-latch-and-gate.vhd

View differences:

vhdl_json/vhdl_files/2-exportOK/valencia/d-latch-and-gate.vhd
54 54
    y <= a and b after 2ns;
55 55
    wait;
56 56
  end process and2_behavior;
57
gnd architecture basic;
57
end architecture basic;
58 58

  
59 59
-- Main archi
60 60
architecture struct of reg4 is
61 61
  signal int_clk: bit;
62 62
  begin
63
    q0 <= d0 & d1;
64
    q1 <= d2 & d3;
63 65
    bit0: entity work.d_latch(basic)
64 66
    port map (d0, int_clk, q0);
65 67
    bit1: entity work.d_latch(basic)

Also available in: Unified diff