Revision 1a2296da vhdl_json/vhdl_files/2-exportOK/valencia/d-latch-and-gate.vhd
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y <= a and b after 2ns; |
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wait; |
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end process and2_behavior; |
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gnd architecture basic;
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end architecture basic;
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-- Main archi |
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architecture struct of reg4 is |
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signal int_clk: bit; |
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begin |
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q0 <= d0 & d1; |
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q1 <= d2 & d3; |
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bit0: entity work.d_latch(basic) |
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port map (d0, int_clk, q0); |
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bit1: entity work.d_latch(basic) |
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