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vhdl_json/vhdl_files/2-exportOK/valencia/d-latch-and-gate.json
308 308
              "name" : ["SIMPLE_NAME", "bit"]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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        ], "ARCHITECTURE_STATEMENT_PART" : [["CONDITIONAL_SIGNAL_ASSIGNMENT", {
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          "postponed" : false, "lhs" : ["SIMPLE_NAME", "q0"], "rhs" : [{
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            "expr" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "id" : "&", "args" : [["EXPRESSION", {
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                        "args" : [["CALL", ["SIMPLE_NAME", "d0"]]]}
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                      ], ["EXPRESSION", {
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                        "args" : [["CALL", ["SIMPLE_NAME", "d1"]]]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ]}
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        ], ["CONDITIONAL_SIGNAL_ASSIGNMENT", {
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          "postponed" : false, "lhs" : ["SIMPLE_NAME", "q1"], "rhs" : [{
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            "expr" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "id" : "&", "args" : [["EXPRESSION", {
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                        "args" : [["CALL", ["SIMPLE_NAME", "d2"]]]}
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                      ], ["EXPRESSION", {
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                        "args" : [["CALL", ["SIMPLE_NAME", "d3"]]]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "bit0"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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            "actual_designator" : ["SIMPLE_NAME", "d0"]}
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          , {
vhdl_json/vhdl_files/2-exportOK/valencia/d-latch-and-gate.vhd
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    y <= a and b after 2ns;
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    wait;
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  end process and2_behavior;
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gnd architecture basic;
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end architecture basic;
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-- Main archi
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architecture struct of reg4 is
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  signal int_clk: bit;
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  begin
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    q0 <= d0 & d1;
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    q1 <= d2 & d3;
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    bit0: entity work.d_latch(basic)
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    port map (d0, int_clk, q0);
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    bit1: entity work.d_latch(basic)

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