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-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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library ieee;  use ieee.std_logic_1164.all;
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entity reg_ctrl is
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  port ( reg_addr_decoded, rd, wr, io_en, cpu_clk : in std_ulogic;
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         reg_rd, reg_wr : out std_ulogic );
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end entity reg_ctrl;
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--------------------------------------------------
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architecture bool_eqn of reg_ctrl is
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begin
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  rd_ctrl : reg_rd <= reg_addr_decoded and rd and io_en;
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  rw_ctrl : reg_wr <= reg_addr_decoded and wr and io_en
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                      and not cpu_clk;
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end architecture bool_eqn;
(12-12/12)