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-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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entity inline_01 is
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end entity inline_01;
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----------------------------------------------------------------
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architecture test of inline_01 is
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begin
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  process_2_a : process is
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    type t1 is (t1_1, t1_2);
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    type t2 is (t2_1, t2_2);
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    type t3 is (t3_1, t3_2);
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    type t4 is (t4_1, t4_2);
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    constant v4 : t4 := t4_1;
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    constant val1 : t1 := t1_1;
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    constant val2 : t2 := t2_1;
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    variable var3 : t3 := t3_1;
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    constant val4 : t4 := t4_1;
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    -- code from book:
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    procedure p ( f1 : in t1;  f2 : in t2;  f3 : out t3;  f4 : in t4 := v4 ) is
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    begin
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      -- . . .
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    end procedure p;
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    -- end of code from book
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  begin
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    -- code from book:
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    p ( val1, val2, var3, val4 );
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    p ( f1 => val1, f2 => val2, f4 => val4, f3 => var3 );
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    p ( val1, val2, f4 => open, f3 => var3 );
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    p ( val1, val2, var3 );
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    -- end of code from book
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    wait;
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  end process process_2_a;
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end architecture test;
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