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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "D_flipflop"], "ports" : [{
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          "names" : [["IDENTIFIER", "clk"], ["IDENTIFIER", "d"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "bit"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "q"]], "mode" : ["buffer"], "typ" : {
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            "name" : ["SIMPLE_NAME", "bit"]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "behavioral"], "entity" : ["IDENTIFIER", "D_flipflop"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : [["CONDITIONAL_SIGNAL_ASSIGNMENT", {
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          "postponed" : false, "lhs" : ["SIMPLE_NAME", "q"], "rhs" : [{
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            "expr" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CALL", ["SIMPLE_NAME", "d"]]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ], "cond" : ["EXPRESSION", {
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              "id" : "and", "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CALL", ["ATTRIBUTE_NAME", {
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                        "id" : ["SIMPLE_NAME", "clk"], "designator" : ["SIMPLE_NAME", "event"]}
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                      ]]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ], ["EXPRESSION", {
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                "id" : "=", "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CALL", ["SIMPLE_NAME", "clk"]]]}
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                    ]]}
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                  ]]}
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                ], ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "'1'"]}
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                      ]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          ]}
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        ]]}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "inverter"], "ports" : [{
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          "names" : [["IDENTIFIER", "a"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "bit"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "y"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "bit"]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "behavioral"], "entity" : ["IDENTIFIER", "inverter"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : [["CONDITIONAL_SIGNAL_ASSIGNMENT", {
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          "postponed" : false, "lhs" : ["SIMPLE_NAME", "y"], "rhs" : [{
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            "expr" : [{
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              "value" : ["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "id" : "not", "args" : [["CALL", ["SIMPLE_NAME", "a"]]]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]}
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            ]}
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          ]}
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        ]]}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "count2"], "ports" : [{
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          "names" : [["IDENTIFIER", "clk"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "bit"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "q0"], ["IDENTIFIER", "q1"]], "mode" : ["buffer"], "typ" : {
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            "name" : ["SIMPLE_NAME", "bit"]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "buffered_outputs"], "entity" : ["IDENTIFIER", "count2"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["COMPONENT_DECLARATION", {
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            "name" : ["IDENTIFIER", "D_flipflop"], "ports" : [{
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              "names" : [["IDENTIFIER", "clk"], ["IDENTIFIER", "d"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "bit"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "q"]], "mode" : ["buffer"], "typ" : {
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                "name" : ["SIMPLE_NAME", "bit"]}
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              }
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            ]}
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          ]}
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        , {
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          "declaration" : ["COMPONENT_DECLARATION", {
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            "name" : ["IDENTIFIER", "inverter"], "ports" : [{
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              "names" : [["IDENTIFIER", "a"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "bit"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "y"]], "mode" : ["out"], "typ" : {
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                "name" : ["SIMPLE_NAME", "bit"]}
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              }
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            ]}
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "q0_n"], ["IDENTIFIER", "q1_n"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "bit"]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "bit0"], "inst_unit" : ["SIMPLE_NAME", "D_flipflop"], "inst_unit_type" : "component", "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "clk"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "d"], "actual_designator" : ["SIMPLE_NAME", "q0_n"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "q"], "actual_designator" : ["SIMPLE_NAME", "q0"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "inv0"], "inst_unit" : ["SIMPLE_NAME", "inverter"], "inst_unit_type" : "component", "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "a"], "actual_designator" : ["SIMPLE_NAME", "q0"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "y"], "actual_designator" : ["SIMPLE_NAME", "q0_n"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "bit1"], "inst_unit" : ["SIMPLE_NAME", "D_flipflop"], "inst_unit_type" : "component", "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "q0_n"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "d"], "actual_designator" : ["SIMPLE_NAME", "q1_n"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "q"], "actual_designator" : ["SIMPLE_NAME", "q1"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "inv1"], "inst_unit" : ["SIMPLE_NAME", "inverter"], "inst_unit_type" : "component", "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "a"], "actual_designator" : ["SIMPLE_NAME", "q1"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "y"], "actual_designator" : ["SIMPLE_NAME", "q1_n"]}
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          ]}
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        ]]}
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      ]}
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    ]}
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  }
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