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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["SIMPLE_NAME", "serial_interface_defs"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "microcontroller"], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]]], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "structure"], "entity" : ["IDENTIFIER", "microcontroller"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "use_clause" : ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["SIMPLE_NAME", "serial_interface_defs"], ["IDENTIFIER", "serial_interface"]]]]]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "buffered_phi1"], ["IDENTIFIER", "buffered_phi2"], ["IDENTIFIER", "serial_a_select"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic"]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "internal_addr"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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                "ranges" : [["RANGE_WITH_DIRECTION", {
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                  "direction" : "downto", "from" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "1"]}
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                      ]]}
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                    ]]}
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                  ], "_to" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "0"]}
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                      ]]}
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                    ]]}
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                  ]}
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                ]]}
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              ]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "internal_data_bus"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "data_vector"]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "serial_a_int_req"], ["IDENTIFIER", "rx_data_a"], ["IDENTIFIER", "tx_data_a"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic"]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "serial_a"], "inst_unit" : ["SIMPLE_NAME", "serial_interface"], "inst_unit_type" : "component", "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "clock_phi1"], "actual_designator" : ["SIMPLE_NAME", "buffered_phi1"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "clock_phi2"], "actual_designator" : ["SIMPLE_NAME", "buffered_phi2"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "serial_select"], "actual_designator" : ["SIMPLE_NAME", "serial_a_select"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "reg_address"], "actual_designator" : ["SLICE_NAME", {
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              "id" : ["SIMPLE_NAME", "internal_addr"], "range" : ["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "1"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]}
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            ]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "data"], "actual_designator" : ["SIMPLE_NAME", "internal_data_bus"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "interrupt_request"], "actual_designator" : ["SIMPLE_NAME", "serial_a_int_req"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "rx_serial_data"], "actual_designator" : ["SIMPLE_NAME", "rx_data_a"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "tx_serial_data"], "actual_designator" : ["SIMPLE_NAME", "tx_data_a"]}
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          ]}
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        ]]}
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      ]}
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    ]}
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  }
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