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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["SIMPLE_NAME", "MVL4"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "ROM"], "ports" : [{
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          "names" : [["IDENTIFIER", "a"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "MVL4_ulogic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "15"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "d"]], "mode" : ["inout"], "typ" : {
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            "name" : ["SIMPLE_NAME", "MVL4_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "7"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "rd"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "MVL4_ulogic"]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "behavioral"], "entity" : ["IDENTIFIER", "ROM"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["SIMPLE_NAME", "MVL4"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "SIMM"], "ports" : [{
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          "names" : [["IDENTIFIER", "a"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "MVL4_ulogic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "9"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "d"]], "mode" : ["inout"], "typ" : {
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            "name" : ["SIMPLE_NAME", "MVL4_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "31"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "ras"], ["IDENTIFIER", "cas"], ["IDENTIFIER", "we"], ["IDENTIFIER", "cs"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "MVL4_ulogic"]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "behavioral"], "entity" : ["IDENTIFIER", "SIMM"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["SIMPLE_NAME", "MVL4"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "memory_subsystem"], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "detailed"], "entity" : ["IDENTIFIER", "memory_subsystem"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "internal_data"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "MVL4_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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                "ranges" : [["RANGE_WITH_DIRECTION", {
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                  "direction" : "downto", "from" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "31"]}
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                      ]]}
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                    ]]}
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                  ], "_to" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "0"]}
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                      ]]}
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                    ]]}
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                  ]}
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                ]]}
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              ]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "internal_addr"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "MVL4_ulogic_vector"], "const" : ["INDEX_CONSTRAINT", {
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                "ranges" : [["RANGE_WITH_DIRECTION", {
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                  "direction" : "downto", "from" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "31"]}
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                      ]]}
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                    ]]}
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                  ], "_to" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "0"]}
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                      ]]}
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                    ]]}
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                  ]}
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                ]]}
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              ]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "main_mem_addr"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "MVL4_ulogic_vector"], "const" : ["INDEX_CONSTRAINT", {
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                "ranges" : [["RANGE_WITH_DIRECTION", {
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                  "direction" : "downto", "from" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "9"]}
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                      ]]}
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                    ]]}
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                  ], "_to" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "0"]}
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                      ]]}
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                    ]]}
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                  ]}
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                ]]}
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              ]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "ROM_select"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "MVL4_ulogic"]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "boot_ROM"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "ROM"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "behavioral"], "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "a"], "actual_designator" : ["SLICE_NAME", {
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              "id" : ["SIMPLE_NAME", "internal_addr"], "range" : ["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "15"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]}
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            ]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "d"], "actual_designator" : ["SLICE_NAME", {
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              "id" : ["SIMPLE_NAME", "internal_data"], "range" : ["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "7"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]}
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            ]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "rd"], "actual_designator" : ["SIMPLE_NAME", "ROM_select"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "main_mem"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "SIMM"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "behavioral"], "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "a"], "actual_designator" : ["SIMPLE_NAME", "main_mem_addr"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "d"], "actual_designator" : ["SIMPLE_NAME", "internal_data"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "ras"], "actual_expr" : ["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "'0'"]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "cas"], "actual_expr" : ["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "'0'"]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "we"], "actual_expr" : ["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "'0'"]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "cs"], "actual_expr" : ["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "'0'"]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          ]}
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        ]]}
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      ]}
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    ]}
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  }
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