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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "bus_sequencer"], "ports" : [{
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          "names" : [["IDENTIFIER", "rd"], ["IDENTIFIER", "wr"], ["IDENTIFIER", "sel"], ["IDENTIFIER", "width"], ["IDENTIFIER", "burst"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_ulogic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "addr_low_2"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_ulogic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "1"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "ready"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_ulogic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "control_reg_wr"], ["IDENTIFIER", "status_reg_rd"], ["IDENTIFIER", "data_fifo_wr"], ["IDENTIFIER", "data_fifo_rd"], ["IDENTIFIER", "other_signal"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_ulogic"]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "state_register"], "ports" : [{
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          "names" : [["IDENTIFIER", "phi1"], ["IDENTIFIER", "phi2"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_ulogic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "next_state"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_ulogic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "3"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "current_state"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_ulogic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "3"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "std_cell"], "entity" : ["IDENTIFIER", "state_register"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "fsm"], "entity" : ["IDENTIFIER", "bus_sequencer"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "next_state_vector"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_ulogic_vector"], "const" : ["INDEX_CONSTRAINT", {
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                "ranges" : [["RANGE_WITH_DIRECTION", {
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                  "direction" : "downto", "from" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "3"]}
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                      ]]}
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                    ]]}
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                  ], "_to" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "0"]}
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                      ]]}
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                    ]]}
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                  ]}
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                ]]}
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              ]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "current_state_vector"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_ulogic_vector"], "const" : ["INDEX_CONSTRAINT", {
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                "ranges" : [["RANGE_WITH_DIRECTION", {
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                  "direction" : "downto", "from" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "3"]}
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                      ]]}
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                    ]]}
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                  ], "_to" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "0"]}
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                      ]]}
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                    ]]}
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                  ]}
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                ]]}
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              ]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "bus_sequencer_state_register"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "state_register"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "std_cell"], "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "phi1"], "actual_designator" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["SIMPLE_NAME", "clock_pkg"], ["IDENTIFIER", "clock_phase1"]]]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "phi2"], "actual_designator" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["SIMPLE_NAME", "clock_pkg"], ["IDENTIFIER", "clock_phase2"]]]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "next_state"], "actual_designator" : ["SIMPLE_NAME", "next_state_vector"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "current_state"], "actual_designator" : ["SIMPLE_NAME", "current_state_vector"]}
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          ]}
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        ]]}
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      ]}
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    ]}
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  }
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