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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "widget_cells"], ["IDENTIFIER", "wasp_lib"]]]], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "cell_based"], "entity" : ["IDENTIFIER", "filter"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "clk"], ["IDENTIFIER", "filter_clk"], ["IDENTIFIER", "accum_en"], ["IDENTIFIER", "carry"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "bit"]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "sum"], ["IDENTIFIER", "alu_op1"], ["IDENTIFIER", "alu_op2"], ["IDENTIFIER", "result"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "bit_vector"], "const" : ["INDEX_CONSTRAINT", {
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                "ranges" : [["RANGE_WITH_DIRECTION", {
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                  "direction" : "downto", "from" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "31"]}
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                      ]]}
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                    ]]}
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                  ], "_to" : ["EXPRESSION", {
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                    "args" : [["EXPRESSION", {
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                      "args" : [["CONSTANT_VALUE", {
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                        "value" : ["CST_LITERAL", "0"]}
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                      ]]}
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                    ]]}
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                  ]}
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                ]]}
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              ]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "clk_pad"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "wasp_lib"], ["IDENTIFIER", "in_pad"]]], "inst_unit_type" : "entity", "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "i"], "actual_designator" : ["SIMPLE_NAME", "clk"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "z"], "actual_designator" : ["SIMPLE_NAME", "filter_clk"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "accum"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "widget_cells"], ["IDENTIFIER", "reg32"]]], "inst_unit_type" : "entity", "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "en"], "actual_designator" : ["SIMPLE_NAME", "accum_en"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "filter_clk"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "d"], "actual_designator" : ["SIMPLE_NAME", "sum"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "q"], "actual_designator" : ["SIMPLE_NAME", "result"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "alu"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "adder"]]], "inst_unit_type" : "entity", "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "a"], "actual_designator" : ["SIMPLE_NAME", "alu_op1"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "b"], "actual_designator" : ["SIMPLE_NAME", "alu_op2"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "y"], "actual_designator" : ["SIMPLE_NAME", "sum"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "c"], "actual_designator" : ["SIMPLE_NAME", "carry"]}
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          ]}
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        ]]}
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      ]}
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    ]}
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  }
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