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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "numeric_std"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "wrapper"], "ports" : [{
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          "names" : [["IDENTIFIER", "clk"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "reset"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "write"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "ack"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "a"], "entity" : ["IDENTIFIER", "wrapper"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["COMPONENT_DECLARATION", {
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            "name" : ["IDENTIFIER", "write"], "ports" : [{
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              "names" : [["IDENTIFIER", "clk"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "reset"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "write"]], "mode" : ["in"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            , {
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              "names" : [["IDENTIFIER", "ack"]], "mode" : ["out"], "typ" : {
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                "name" : ["SIMPLE_NAME", "std_logic"]}
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              }
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            ]}
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "dut"], "inst_unit" : ["SIMPLE_NAME", "write"], "inst_unit_type" : "component", "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "clk"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "reset"], "actual_designator" : ["SIMPLE_NAME", "reset"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "write"], "actual_designator" : ["SIMPLE_NAME", "write"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "ack"], "actual_designator" : ["SIMPLE_NAME", "ack"]}
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          ]}
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        ]]}
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      ]}
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    ]}
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  }
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