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library ieee;
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use ieee.std_logic_1164.all;
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library ieee;
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use ieee.numeric_std.all;
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entity w_split7 is
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	port (
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		clk : in  std_logic;
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		ra0_data : out std_logic_vector(7 downto 0);
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		wa0_data : in  std_logic_vector(7 downto 0);
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		wa0_addr : in  std_logic;
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		wa0_en : in  std_logic;
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		ra0_addr : in  std_logic
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	);
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end w_split7;
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architecture augh of w_split7 is
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	-- Embedded RAM
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	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
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	signal ram : ram_type := (
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		"00000111", "00000111"
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	);
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	-- Little utility functions to make VHDL syntactically correct
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	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
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	--   This happens when accessing arrays with <= 2 cells, for example.
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	function to_integer(B: std_logic) return integer is
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		variable V: std_logic_vector(0 to 0);
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	begin
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		V(0) := B;
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		return to_integer(unsigned(V));
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	end;
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	function to_integer(V: std_logic_vector) return integer is
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	begin
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		return to_integer(unsigned(V));
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	end;
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begin
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	-- Sequential process
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	-- It handles the Writes
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	process (clk)
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	begin
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		if rising_edge(clk) then
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			-- Write to the RAM
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			-- Note: there should be only one port.
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			if wa0_en = '1' then
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				ram( to_integer(wa0_addr) ) <= wa0_data;
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			end if;
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		end if;
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	end process;
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	-- The Read side (the outputs)
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	ra0_data <= ram( to_integer(ra0_addr) );
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end architecture;
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