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--test bench written by Alban Bourge @ TIMA
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.pkg_tb.all;
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entity prog is
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port(
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clock : in std_logic;
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reset : in std_logic;
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step : in std_logic;
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instr_next : out instruction
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);
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end prog;
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architecture rtl of prog is
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signal instr_n : instruction := instr_rst;
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--Table describing fsm behavior
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constant fsm_behavior : table_behavior := (
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--##PROGRAM_GOES_DOWN_HERE##--
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0 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
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1 => (state => Rst, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
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2 => (state => Sig_start, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
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3 => (state => Ack_data, context_uut => "01", arg => to_unsigned(2,ARG_WIDTH)),
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4 => (state => Running, context_uut => "01", arg => to_unsigned(5,ARG_WIDTH)),
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5 => (state => Cp_search, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
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6 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
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7 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
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8 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
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9 => (state => Sig_start, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
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10 => (state => Ack_data, context_uut => "10", arg => to_unsigned(2,ARG_WIDTH)),
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11 => (state => Running, context_uut => "10", arg => to_unsigned(6,ARG_WIDTH)),
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12 => (state => Cp_search, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
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13 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
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14 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
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15 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
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16 => (state => Rest_ini0, context_uut => "01", arg => to_unsigned(0,ARG_WIDTH)),
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17 => (state => Waitfor, context_uut => "01", arg => to_unsigned(1,ARG_WIDTH)),
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18 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
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19 => (state => Rst_uut, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
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20 => (state => Idle, context_uut => "00", arg => to_unsigned(5,ARG_WIDTH)),
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21 => (state => Rest_ini0, context_uut => "10", arg => to_unsigned(0,ARG_WIDTH)),
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22 => (state => Waitfor, context_uut => "10", arg => to_unsigned(1,ARG_WIDTH)),
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23 => (state => Stop, context_uut => "00", arg => to_unsigned(0,ARG_WIDTH)),
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--##PROGRAM_GOES_OVER_HERE##--
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others => instr_rst);
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signal pc : unsigned(PC_SIZE - 1 downto 0) := (others => '0');
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begin
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drive_state : process (reset,clock) is
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begin
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if reset = '1' then
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instr_n <= instr_rst;
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pc <= (others => '0');
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elsif rising_edge(clock) then
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if (step = '1') then
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pc <= pc + 1;
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end if;
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instr_n <= fsm_behavior(to_integer(pc));
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end if;
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end process drive_state;
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--instr_next <= instr_n;
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instr_next <= fsm_behavior(to_integer(pc));
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end rtl;
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