lustrec-tests/vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/gna/issue50/vector.d/cmp_142.vhd @ ddabd63e
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library ieee; |
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use ieee.std_logic_1164.all; |
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entity cmp_142 is |
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port ( |
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eq : out std_logic; |
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in0 : in std_logic_vector(2 downto 0); |
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in1 : in std_logic_vector(2 downto 0) |
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);
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end cmp_142; |
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architecture augh of cmp_142 is |
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signal tmp : std_logic; |
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begin
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-- Compute the result
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tmp <= |
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'0' when in0 /= in1 else |
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'1'; |
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-- Set the outputs
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eq <= tmp; |
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end architecture; |