CristalCaveGem » LustreC » Lustrec-Tests

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-- Company   : CNES

-- Author    : Mickael Carl (CNES)

-- Copyright : Copyright (c) CNES. 

-- Licensing : GNU GPLv3

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-- Version         : V1

-- Version history : 

--    V1 : 2015-04-15 : Mickael Carl (CNES): Creation

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-- File name          : CNE_02300_bad.vhd

-- File Creation date : 2015-04-15

-- Project name       : VHDL Handbook CNES Edition 

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-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)

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-- Description : Handbook example: Preservation of clock name: bad example

--

-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at

--               demonstrating good practices in VHDL and as such, its design is minimalistic.

--               It is provided as is, without any warranty.

--               This example is compliant with the Handbook version 1.

--

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-- Naming conventions: 

--

-- i_Port: Input entity port

-- o_Port: Output entity port

-- b_Port: Bidirectional entity port

-- g_My_Generic: Generic entity port

--

-- c_My_Constant: Constant definition 

-- t_My_Type: Custom type definition

--

-- My_Signal_n: Active low signal

-- v_My_Variable: Variable

-- sm_My_Signal: FSM signal

-- pkg_Param: Element Param coming from a package

--

-- My_Signal_re: Rising edge detection of My_Signal

-- My_Signal_fe: Falling edge detection of My_Signal

-- My_Signal_rX: X times registered My_Signal signal

--

-- P_Process_Name: Process

--

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library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

library work;

use work.pkg_HBK.all;

--CODE

entity CNE_02300_bad is

   port  (

      i_Clk       : in std_logic;   -- Clock signal

      i_Reset_n   : in std_logic;   -- Reset signal

      i_D         : in std_logic;   -- D Flip-Flop input signal

      o_Q         : out std_logic   -- D Flip-Flop output signal

   );

end CNE_02300_bad;

architecture Behavioral of CNE_02300_bad is

   signal Clock_tmp : std_logic;

begin

   Clock_tmp <= i_Clk;

   DFF1:DFlipFlop

   port map (

      i_Clock     => Clock_tmp,

      i_Reset_n   => i_Reset_n,

      i_D         => i_D,

      o_Q         => o_Q,

      o_Q_n       => open

   );

end Behavioral;

--CODE