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{
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  "DESIGN_FILE" : {
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    "design_units" : [{
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      "contexts" : [["LIBRARY_CLAUSE", [["IDENTIFIER", "ieee"]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_1164"]]]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "ieee"], ["SIMPLE_NAME", "std_logic_unsigned"]]]]], ["USE_CLAUSE", [["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["SIMPLE_NAME", "plasmaPeriphRegisters"]]]]]], "library" : ["ENTITY_DECLARATION", {
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        "name" : ["IDENTIFIER", "PlasmaBlockRam"], "generics" : [{
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          "names" : [["IDENTIFIER", "uartLogFile"]], "typ" : {
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            "name" : ["SIMPLE_NAME", "string"]}
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          , "expr" : ["EXPRESSION", {
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            "args" : [["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["CONSTANT_VALUE", {
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                    "value" : ["CST_LITERAL", "\"UNUSED\""]}
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                  ]]}
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                ]]}
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              ]]}
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            ]]}
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          ]}
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        , {
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          "names" : [["IDENTIFIER", "simulateRam"]], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          , "expr" : ["EXPRESSION", {
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            "args" : [["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["CONSTANT_VALUE", {
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                    "value" : ["CST_LITERAL", "'0'"]}
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                  ]]}
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                ]]}
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              ]]}
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            ]]}
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          ]}
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        , {
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          "names" : [["IDENTIFIER", "simulateProgram"]], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          , "expr" : ["EXPRESSION", {
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            "args" : [["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["CONSTANT_VALUE", {
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                    "value" : ["CST_LITERAL", "'0'"]}
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                  ]]}
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                ]]}
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              ]]}
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            ]]}
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          ]}
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        ], "ports" : [{
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          "names" : [["IDENTIFIER", "clk_100"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "reset_ex_n"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "UartRx"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          , "expr" : ["EXPRESSION", {
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            "args" : [["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["CONSTANT_VALUE", {
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                    "value" : ["CST_LITERAL", "'1'"]}
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                  ]]}
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                ]]}
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              ]]}
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            ]]}
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          ]}
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        , {
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          "names" : [["IDENTIFIER", "UartTx"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "leds"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "7"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "switches"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "7"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "buttons"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "4"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "pmod"]], "mode" : ["inout"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "7"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "Uart_bypassRx"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "7"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          , "expr" : ["EXPRESSION", {
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            "args" : [["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["AGGREGATE", {
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                    "elems" : [{
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                      "choices" : [["OTHERS"]], "expr" : ["EXPRESSION", {
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                        "args" : [["EXPRESSION", {
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                          "args" : [["EXPRESSION", {
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                            "args" : [["EXPRESSION", {
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                              "args" : [["CONSTANT_VALUE", {
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                                "value" : ["CST_LITERAL", "'0'"]}
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                              ]]}
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                            ]]}
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                          ]]}
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                        ]]}
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                      ]}
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                    ]}
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                  ]]}
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                ]]}
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              ]]}
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            ]]}
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          ]}
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        , {
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          "names" : [["IDENTIFIER", "Uart_bypassRxWeToggle"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          , "expr" : ["EXPRESSION", {
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            "args" : [["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["CONSTANT_VALUE", {
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                    "value" : ["CST_LITERAL", "'0'"]}
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                  ]]}
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                ]]}
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              ]]}
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            ]]}
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          ]}
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        , {
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          "names" : [["IDENTIFIER", "Uart_bypassTx"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "7"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "Uart_bypassTxDvToggle"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "FifoDin"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "31"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          , "expr" : ["EXPRESSION", {
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            "args" : [["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["AGGREGATE", {
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                    "elems" : [{
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                      "choices" : [["OTHERS"]], "expr" : ["EXPRESSION", {
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                        "args" : [["EXPRESSION", {
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                          "args" : [["EXPRESSION", {
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                            "args" : [["EXPRESSION", {
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                              "args" : [["CONSTANT_VALUE", {
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                                "value" : ["CST_LITERAL", "'0'"]}
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                              ]]}
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                            ]]}
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                          ]]}
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                        ]]}
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                      ]}
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                    ]}
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                  ]]}
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                ]]}
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              ]]}
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            ]]}
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          ]}
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        , {
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          "names" : [["IDENTIFIER", "FifoDout"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "31"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "FifoWe"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          , "expr" : ["EXPRESSION", {
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            "args" : [["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["CONSTANT_VALUE", {
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                    "value" : ["CST_LITERAL", "'0'"]}
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                  ]]}
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                ]]}
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              ]]}
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            ]]}
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          ]}
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        , {
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          "names" : [["IDENTIFIER", "FifoRe"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          , "expr" : ["EXPRESSION", {
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            "args" : [["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["CONSTANT_VALUE", {
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                    "value" : ["CST_LITERAL", "'0'"]}
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                  ]]}
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                ]]}
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              ]]}
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            ]]}
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          ]}
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        , {
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          "names" : [["IDENTIFIER", "FifoFull"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "FifoEmpty"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "FifoClear"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          , "expr" : ["EXPRESSION", {
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            "args" : [["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["CONSTANT_VALUE", {
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                    "value" : ["CST_LITERAL", "'0'"]}
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                  ]]}
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                ]]}
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              ]]}
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            ]]}
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          ]}
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        , {
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          "names" : [["IDENTIFIER", "ExBusDin"]], "mode" : ["in"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "31"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          , "expr" : ["EXPRESSION", {
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            "args" : [["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["AGGREGATE", {
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                    "elems" : [{
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                      "choices" : [["OTHERS"]], "expr" : ["EXPRESSION", {
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                        "args" : [["EXPRESSION", {
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                          "args" : [["EXPRESSION", {
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                            "args" : [["EXPRESSION", {
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                              "args" : [["CONSTANT_VALUE", {
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                                "value" : ["CST_LITERAL", "'0'"]}
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                              ]]}
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                            ]]}
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                          ]]}
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                        ]]}
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                      ]}
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                    ]}
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                  ]]}
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                ]]}
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              ]]}
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            ]]}
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          ]}
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        , {
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          "names" : [["IDENTIFIER", "ExBusDout"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "31"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "ExBusAddr"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
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                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "31"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "ExBusRe"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "ExBusWe"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "FlashCLK"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "FlashCS"]], "mode" : ["out"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic"]}
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          }
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        , {
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          "names" : [["IDENTIFIER", "FlashMemDq"]], "mode" : ["inout"], "typ" : {
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            "name" : ["SIMPLE_NAME", "std_logic_vector"], "const" : ["INDEX_CONSTRAINT", {
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              "ranges" : [["RANGE_WITH_DIRECTION", {
447
                "direction" : "downto", "from" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "3"]}
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                    ]]}
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                  ]]}
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                ], "_to" : ["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "0"]}
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                    ]]}
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                  ]]}
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                ]}
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              ]]}
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            ]}
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          }
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        ], "ENTITY_DECLARATIVE_PART" : [], "ENTITY_STATEMENT_PART" : []}
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      ]}
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    , {
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      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
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        "name" : ["IDENTIFIER", "logic"], "entity" : ["IDENTIFIER", "PlasmaBlockRam"], "ARCHITECTURE_DECLARATIVE_PART" : [{
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "sysClk"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic"]}
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            }
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          ]}
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        , {
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          "declaration" : ["SIGNAL_DECLARATION", {
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            "names" : [["IDENTIFIER", "reset_n"]], "typ" : {
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              "name" : ["SIMPLE_NAME", "std_logic"]}
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            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "MCU"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "PlasmaTop"]]], "inst_unit_type" : "entity", "generic_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "uartLogFile"], "actual_designator" : ["SIMPLE_NAME", "uartLogFile"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "simulateRam"], "actual_designator" : ["SIMPLE_NAME", "simulateRam"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "simulateProgram"], "actual_designator" : ["SIMPLE_NAME", "simulateProgram"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "AtlysDDR"], "actual_expr" : ["EXPRESSION", {
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              "args" : [["EXPRESSION", {
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                "args" : [["EXPRESSION", {
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                  "args" : [["EXPRESSION", {
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                    "args" : [["CONSTANT_VALUE", {
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                      "value" : ["CST_LITERAL", "'0'"]}
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                    ]]}
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                  ]]}
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                ]]}
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              ]]}
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            ]}
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          ], "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "clk_100"], "actual_designator" : ["SIMPLE_NAME", "clk_100"]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "reset_ex_n"], "actual_designator" : ["SIMPLE_NAME", "reset_ex_n"]}
502
          , {
503
            "formal_name" : ["SIMPLE_NAME", "sysClk"], "actual_designator" : ["SIMPLE_NAME", "sysClk"]}
504
          , {
505
            "formal_name" : ["SIMPLE_NAME", "reset_n"], "actual_designator" : ["SIMPLE_NAME", "reset_n"]}
506
          , {
507
            "formal_name" : ["SIMPLE_NAME", "UartRx"], "actual_designator" : ["SIMPLE_NAME", "UartRx"]}
508
          , {
509
            "formal_name" : ["SIMPLE_NAME", "UartTx"], "actual_designator" : ["SIMPLE_NAME", "UartTx"]}
510
          , {
511
            "formal_name" : ["SIMPLE_NAME", "Uart_bypassRx"], "actual_designator" : ["SIMPLE_NAME", "Uart_bypassRx"]}
512
          , {
513
            "formal_name" : ["SIMPLE_NAME", "Uart_bypassRxWeToggle"], "actual_designator" : ["SIMPLE_NAME", "Uart_bypassRxWeToggle"]}
514
          , {
515
            "formal_name" : ["SIMPLE_NAME", "Uart_bypassTx"], "actual_designator" : ["SIMPLE_NAME", "Uart_bypassTx"]}
516
          , {
517
            "formal_name" : ["SIMPLE_NAME", "Uart_bypassTxDvToggle"], "actual_designator" : ["SIMPLE_NAME", "Uart_bypassTxDvToggle"]}
518
          , {
519
            "formal_name" : ["SIMPLE_NAME", "leds"], "actual_designator" : ["SIMPLE_NAME", "leds"]}
520
          , {
521
            "formal_name" : ["SIMPLE_NAME", "switches"], "actual_designator" : ["SIMPLE_NAME", "switches"]}
522
          , {
523
            "formal_name" : ["SIMPLE_NAME", "buttons"], "actual_designator" : ["SIMPLE_NAME", "buttons"]}
524
          , {
525
            "formal_name" : ["SIMPLE_NAME", "pmod"], "actual_designator" : ["SIMPLE_NAME", "pmod"]}
526
          , {
527
            "formal_name" : ["SIMPLE_NAME", "FlashClk"], "actual_designator" : ["SIMPLE_NAME", "FlashClk"]}
528
          , {
529
            "formal_name" : ["SIMPLE_NAME", "FlashCS"], "actual_designator" : ["SIMPLE_NAME", "FlashCS"]}
530
          , {
531
            "formal_name" : ["SIMPLE_NAME", "FlashMemDq"], "actual_designator" : ["SIMPLE_NAME", "FlashMemDq"]}
532
          ]}
533
        ]]}
534
      ]}
535
    ]}
536
  }
(3-3/6)