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Revision ddabd63e

Added by Arnaud Dieumegard over 3 years ago

Updated tests for lustrei vhdl import

View differences:

vhdl_json/vhdl_files/2-exportOK/vhd2vl/test.json
1715 1715
            ]]}
1716 1716
          ]]}
1717 1717
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
1718
          "name" : ["IDENTIFIER", "dsp_inst"], "inst_unit" : ["SIMPLE_NAME", "dsp"], "port_map" : [{
1718
          "name" : ["IDENTIFIER", "dsp_inst"], "inst_unit" : ["SIMPLE_NAME", "dsp"], "inst_unit_type" : "component", "port_map" : [{
1719 1719
            "formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "clk"]}
1720 1720
          , {
1721 1721
            "formal_name" : ["SIMPLE_NAME", "rstn"], "actual_designator" : ["SIMPLE_NAME", "rstn"]}
......
1741 1741
            "formal_name" : ["SIMPLE_NAME", "memdout"], "actual_designator" : ["SIMPLE_NAME", "memdout"]}
1742 1742
          ]}
1743 1743
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
1744
          "name" : ["IDENTIFIER", "dsp_mem"], "inst_unit" : ["SIMPLE_NAME", "mem"], "port_map" : [{
1744
          "name" : ["IDENTIFIER", "dsp_mem"], "inst_unit" : ["SIMPLE_NAME", "mem"], "inst_unit_type" : "component", "port_map" : [{
1745 1745
            "formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "clk"]}
1746 1746
          , {
1747 1747
            "formal_name" : ["SIMPLE_NAME", "rstn"], "actual_designator" : ["SIMPLE_NAME", "rstn"]}

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