Project

General

Profile

« Previous | Next » 

Revision ddabd63e

Added by Arnaud Dieumegard over 3 years ago

Updated tests for lustrei vhdl import

View differences:

vhdl_json/vhdl_files/2-exportOK/vhd2vl/genericmap.json
553 553
            }
554 554
          ]}
555 555
        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
556
          "name" : ["IDENTIFIER", "dsp_inst0"], "inst_unit" : ["SIMPLE_NAME", "dsp"], "port_map" : [{
556
          "name" : ["IDENTIFIER", "dsp_inst0"], "inst_unit" : ["SIMPLE_NAME", "dsp"], "inst_unit_type" : "component", "port_map" : [{
557 557
            "formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "clk"]}
558 558
          , {
559 559
            "formal_name" : ["SIMPLE_NAME", "rstn"], "actual_designator" : ["SIMPLE_NAME", "rstn"]}
......
565 565
            "formal_name" : ["SIMPLE_NAME", "memdout"], "actual_designator" : ["SIMPLE_NAME", "memdout"]}
566 566
          ]}
567 567
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
568
          "name" : ["IDENTIFIER", "dsp_inst1"], "inst_unit" : ["SIMPLE_NAME", "dsp"], "generic_map" : [{
568
          "name" : ["IDENTIFIER", "dsp_inst1"], "inst_unit" : ["SIMPLE_NAME", "dsp"], "inst_unit_type" : "component", "generic_map" : [{
569 569
            "formal_name" : ["SIMPLE_NAME", "rst_val"], "actual_expr" : ["EXPRESSION", {
570 570
              "args" : [["EXPRESSION", {
571 571
                "args" : [["EXPRESSION", {

Also available in: Unified diff