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Revision ddabd63e

Added by Arnaud Dieumegard over 3 years ago

Updated tests for lustrei vhdl import

View differences:

vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bus_sequencer-1.json
135 135
            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "bus_sequencer_state_register"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "state_register"]]], "archi_name" : ["IDENTIFIER", "std_cell"], "port_map" : [{
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          "name" : ["IDENTIFIER", "bus_sequencer_state_register"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "state_register"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "std_cell"], "port_map" : [{
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            "formal_name" : ["SIMPLE_NAME", "phi1"], "actual_designator" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["SIMPLE_NAME", "clock_power_pkg"], ["IDENTIFIER", "clock_phase1"]]]}
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          , {
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            "formal_name" : ["SIMPLE_NAME", "phi2"], "actual_designator" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["SIMPLE_NAME", "clock_power_pkg"], ["IDENTIFIER", "clock_phase2"]]]}

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