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Revision ddabd63e

Added by Arnaud Dieumegard over 3 years ago

Updated tests for lustrei vhdl import

View differences:

vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/count2-1.json
133 133
            }
134 134
          ]}
135 135
        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
136
          "name" : ["IDENTIFIER", "bit0"], "inst_unit" : ["SIMPLE_NAME", "D_flipflop"], "port_map" : [{
136
          "name" : ["IDENTIFIER", "bit0"], "inst_unit" : ["SIMPLE_NAME", "D_flipflop"], "inst_unit_type" : "component", "port_map" : [{
137 137
            "formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "clk"]}
138 138
          , {
139 139
            "formal_name" : ["SIMPLE_NAME", "d"], "actual_designator" : ["SIMPLE_NAME", "q0_n"]}
......
141 141
            "formal_name" : ["SIMPLE_NAME", "q"], "actual_designator" : ["SIMPLE_NAME", "q0"]}
142 142
          ]}
143 143
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
144
          "name" : ["IDENTIFIER", "inv0"], "inst_unit" : ["SIMPLE_NAME", "inverter"], "port_map" : [{
144
          "name" : ["IDENTIFIER", "inv0"], "inst_unit" : ["SIMPLE_NAME", "inverter"], "inst_unit_type" : "component", "port_map" : [{
145 145
            "formal_name" : ["SIMPLE_NAME", "a"], "actual_designator" : ["SIMPLE_NAME", "q0"]}
146 146
          , {
147 147
            "formal_name" : ["SIMPLE_NAME", "y"], "actual_designator" : ["SIMPLE_NAME", "q0_n"]}
148 148
          ]}
149 149
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
150
          "name" : ["IDENTIFIER", "bit1"], "inst_unit" : ["SIMPLE_NAME", "D_flipflop"], "port_map" : [{
150
          "name" : ["IDENTIFIER", "bit1"], "inst_unit" : ["SIMPLE_NAME", "D_flipflop"], "inst_unit_type" : "component", "port_map" : [{
151 151
            "formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "q0_n"]}
152 152
          , {
153 153
            "formal_name" : ["SIMPLE_NAME", "d"], "actual_designator" : ["SIMPLE_NAME", "q1_n"]}
......
155 155
            "formal_name" : ["SIMPLE_NAME", "q"], "actual_designator" : ["SIMPLE_NAME", "q1"]}
156 156
          ]}
157 157
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
158
          "name" : ["IDENTIFIER", "inv1"], "inst_unit" : ["SIMPLE_NAME", "inverter"], "port_map" : [{
158
          "name" : ["IDENTIFIER", "inv1"], "inst_unit" : ["SIMPLE_NAME", "inverter"], "inst_unit_type" : "component", "port_map" : [{
159 159
            "formal_name" : ["SIMPLE_NAME", "a"], "actual_designator" : ["SIMPLE_NAME", "q1"]}
160 160
          , {
161 161
            "formal_name" : ["SIMPLE_NAME", "y"], "actual_designator" : ["SIMPLE_NAME", "q1_n"]}

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