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Revision ddabd63e

Added by Arnaud Dieumegard over 3 years ago

Updated tests for lustrei vhdl import

View differences:

vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/single_board_computer.json
147 147
            ]}
148 148
          ]}
149 149
        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
150
          "name" : ["IDENTIFIER", "cpu"], "inst_unit" : ["SIMPLE_NAME", "processor"], "port_map" : [{
150
          "name" : ["IDENTIFIER", "cpu"], "inst_unit" : ["SIMPLE_NAME", "processor"], "inst_unit_type" : "component", "port_map" : [{
151 151
            "formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "sys_clk"]}
152 152
          , {
153 153
            "formal_name" : ["SIMPLE_NAME", "a_d"], "actual_designator" : ["SIMPLE_NAME", "cpu_a_d"]}
......
155 155
            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["SIMPLE_NAME", "open"]}
156 156
          ]}
157 157
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
158
          "name" : ["IDENTIFIER", "main_memory"], "inst_unit" : ["SIMPLE_NAME", "memory"], "port_map" : [{
158
          "name" : ["IDENTIFIER", "main_memory"], "inst_unit" : ["SIMPLE_NAME", "memory"], "inst_unit_type" : "component", "port_map" : [{
159 159
            "formal_name" : ["SIMPLE_NAME", "addr"], "actual_designator" : ["SLICE_NAME", {
160 160
              "id" : ["SIMPLE_NAME", "latched_addr"], "range" : ["RANGE_WITH_DIRECTION", {
161 161
                "direction" : "downto", "from" : ["EXPRESSION", {
......
177 177
            "formal_name" : ["SIMPLE_NAME", "other_port"], "actual_designator" : ["SIMPLE_NAME", "open"]}
178 178
          ]}
179 179
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
180
          "name" : ["IDENTIFIER", "serial_interface_a"], "inst_unit" : ["SIMPLE_NAME", "serial_interface"], "port_map" : [{
180
          "name" : ["IDENTIFIER", "serial_interface_a"], "inst_unit" : ["SIMPLE_NAME", "serial_interface"], "inst_unit_type" : "component", "port_map" : [{
181 181
            "formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "sys_clk"]}
182 182
          , {
183 183
            "formal_name" : ["SIMPLE_NAME", "address"], "actual_designator" : ["SLICE_NAME", {

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