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Revision ddabd63e

Added by Arnaud Dieumegard over 3 years ago

Updated tests for lustrei vhdl import

View differences:

vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_06.json
917 917
            }
918 918
          ]}
919 919
        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
920
          "name" : ["IDENTIFIER", "val0_reg"], "inst_unit" : ["SIMPLE_NAME", "digit_register"], "port_map" : [{
920
          "name" : ["IDENTIFIER", "val0_reg"], "inst_unit" : ["SIMPLE_NAME", "digit_register"], "inst_unit_type" : "component", "port_map" : [{
921 921
            "formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "clk"]}
922 922
          , {
923 923
            "formal_name" : ["SIMPLE_NAME", "clr"], "actual_designator" : ["SIMPLE_NAME", "clr"]}
......
927 927
            "formal_name" : ["SIMPLE_NAME", "q"], "actual_designator" : ["SIMPLE_NAME", "current_val0"]}
928 928
          ]}
929 929
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
930
          "name" : ["IDENTIFIER", "val1_reg"], "inst_unit" : ["SIMPLE_NAME", "digit_register"], "port_map" : [{
930
          "name" : ["IDENTIFIER", "val1_reg"], "inst_unit" : ["SIMPLE_NAME", "digit_register"], "inst_unit_type" : "component", "port_map" : [{
931 931
            "formal_name" : ["SIMPLE_NAME", "clk"], "actual_designator" : ["SIMPLE_NAME", "clk"]}
932 932
          , {
933 933
            "formal_name" : ["SIMPLE_NAME", "clr"], "actual_designator" : ["SIMPLE_NAME", "clr"]}
......
937 937
            "formal_name" : ["SIMPLE_NAME", "q"], "actual_designator" : ["SIMPLE_NAME", "current_val1"]}
938 938
          ]}
939 939
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
940
          "name" : ["IDENTIFIER", "incr0"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "add_1"]]], "archi_name" : ["IDENTIFIER", "boolean_eqn"], "port_map" : [{
940
          "name" : ["IDENTIFIER", "incr0"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "add_1"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "boolean_eqn"], "port_map" : [{
941 941
            "formal_name" : ["SIMPLE_NAME", "d"], "actual_designator" : ["SIMPLE_NAME", "current_val0"]}
942 942
          , {
943 943
            "formal_name" : ["SIMPLE_NAME", "y"], "actual_designator" : ["SIMPLE_NAME", "next_val0"]}
944 944
          ]}
945 945
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
946
          "name" : ["IDENTIFIER", "incr1"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "add_1"]]], "archi_name" : ["IDENTIFIER", "boolean_eqn"], "port_map" : [{
946
          "name" : ["IDENTIFIER", "incr1"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "add_1"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "boolean_eqn"], "port_map" : [{
947 947
            "formal_name" : ["SIMPLE_NAME", "d"], "actual_designator" : ["SIMPLE_NAME", "current_val1"]}
948 948
          , {
949 949
            "formal_name" : ["SIMPLE_NAME", "y"], "actual_designator" : ["SIMPLE_NAME", "next_val1"]}
950 950
          ]}
951 951
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
952
          "name" : ["IDENTIFIER", "buf0"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "buf4"]]], "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
952
          "name" : ["IDENTIFIER", "buf0"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "buf4"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
953 953
            "formal_name" : ["SIMPLE_NAME", "a"], "actual_designator" : ["SIMPLE_NAME", "current_val0"]}
954 954
          , {
955 955
            "formal_name" : ["SIMPLE_NAME", "y"], "actual_designator" : ["SIMPLE_NAME", "q0"]}
956 956
          ]}
957 957
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
958
          "name" : ["IDENTIFIER", "buf1"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "buf4"]]], "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
958
          "name" : ["IDENTIFIER", "buf1"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "buf4"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
959 959
            "formal_name" : ["SIMPLE_NAME", "a"], "actual_designator" : ["SIMPLE_NAME", "current_val1"]}
960 960
          , {
961 961
            "formal_name" : ["SIMPLE_NAME", "y"], "actual_designator" : ["SIMPLE_NAME", "q1"]}

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