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Revision ddabd63e

Added by Arnaud Dieumegard over 3 years ago

Updated tests for lustrei vhdl import

View differences:

vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_11.json
9 9
            }
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          ]}
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        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
12
          "name" : ["IDENTIFIER", "bit0"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
12
          "name" : ["IDENTIFIER", "bit0"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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            "actual_designator" : ["SIMPLE_NAME", "d0"]}
14 14
          , {
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            "actual_designator" : ["SIMPLE_NAME", "int_clk"]}
......
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            "actual_designator" : ["SIMPLE_NAME", "q0"]}
18 18
          ]}
19 19
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "bit1"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
20
          "name" : ["IDENTIFIER", "bit1"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
21 21
            "actual_designator" : ["SIMPLE_NAME", "d1"]}
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          , {
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            "actual_designator" : ["SIMPLE_NAME", "int_clk"]}
......
25 25
            "actual_designator" : ["SIMPLE_NAME", "q1"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "bit2"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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          "name" : ["IDENTIFIER", "bit2"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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            "actual_designator" : ["SIMPLE_NAME", "d2"]}
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          , {
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            "actual_designator" : ["SIMPLE_NAME", "int_clk"]}
......
33 33
            "actual_designator" : ["SIMPLE_NAME", "q2"]}
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          ]}
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        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "bit3"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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          "name" : ["IDENTIFIER", "bit3"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "d_latch"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
37 37
            "actual_designator" : ["SIMPLE_NAME", "d3"]}
38 38
          , {
39 39
            "actual_designator" : ["SIMPLE_NAME", "int_clk"]}
......
41 41
            "actual_designator" : ["SIMPLE_NAME", "q3"]}
42 42
          ]}
43 43
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
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          "name" : ["IDENTIFIER", "gate"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "and2"]]], "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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          "name" : ["IDENTIFIER", "gate"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "and2"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "basic"], "port_map" : [{
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            "actual_designator" : ["SIMPLE_NAME", "en"]}
46 46
          , {
47 47
            "actual_designator" : ["SIMPLE_NAME", "clk"]}

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