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Revision ddabd63e

Added by Arnaud Dieumegard over 3 years ago

Updated tests for lustrei vhdl import

View differences:

vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/gna/issue50/vector.d/cp3_test.json
413 413
            ]}
414 414
          ]}
415 415
        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
416
          "name" : ["IDENTIFIER", "uut"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "top"]]], "archi_name" : ["IDENTIFIER", "augh"], "port_map" : [{
416
          "name" : ["IDENTIFIER", "uut"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "top"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "augh"], "port_map" : [{
417 417
            "formal_name" : ["SIMPLE_NAME", "clock"], "actual_designator" : ["SIMPLE_NAME", "clock"]}
418 418
          , {
419 419
            "formal_name" : ["SIMPLE_NAME", "reset"], "actual_designator" : ["SIMPLE_NAME", "reset_top"]}
......
443 443
            "formal_name" : ["SIMPLE_NAME", "stdout_ack"], "actual_designator" : ["SIMPLE_NAME", "stdout_ack"]}
444 444
          ]}
445 445
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
446
          "name" : ["IDENTIFIER", "ram1"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "sync_ram"]]], "archi_name" : ["IDENTIFIER", "rtl"], "port_map" : [{
446
          "name" : ["IDENTIFIER", "ram1"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "sync_ram"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "rtl"], "port_map" : [{
447 447
            "formal_name" : ["SIMPLE_NAME", "clock"], "actual_designator" : ["SIMPLE_NAME", "clock"]}
448 448
          , {
449 449
            "formal_name" : ["SIMPLE_NAME", "we"], "actual_designator" : ["SELECTED_NAME", [["SIMPLE_NAME", "ram_1"], ["IDENTIFIER", "we"]]]}
......
455 455
            "formal_name" : ["SIMPLE_NAME", "dataout"], "actual_designator" : ["SIMPLE_NAME", "dout1"]}
456 456
          ]}
457 457
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
458
          "name" : ["IDENTIFIER", "ram2"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "sync_ram"]]], "archi_name" : ["IDENTIFIER", "rtl"], "port_map" : [{
458
          "name" : ["IDENTIFIER", "ram2"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "sync_ram"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "rtl"], "port_map" : [{
459 459
            "formal_name" : ["SIMPLE_NAME", "clock"], "actual_designator" : ["SIMPLE_NAME", "clock"]}
460 460
          , {
461 461
            "formal_name" : ["SIMPLE_NAME", "we"], "actual_designator" : ["SELECTED_NAME", [["SIMPLE_NAME", "ram_2"], ["IDENTIFIER", "we"]]]}
......
467 467
            "formal_name" : ["SIMPLE_NAME", "dataout"], "actual_designator" : ["SIMPLE_NAME", "dout2"]}
468 468
          ]}
469 469
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
470
          "name" : ["IDENTIFIER", "fsm_unit"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fsm"]]], "archi_name" : ["IDENTIFIER", "rtl"], "port_map" : [{
470
          "name" : ["IDENTIFIER", "fsm_unit"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fsm"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "rtl"], "port_map" : [{
471 471
            "formal_name" : ["SIMPLE_NAME", "clock"], "actual_designator" : ["SIMPLE_NAME", "clock"]}
472 472
          , {
473 473
            "formal_name" : ["SIMPLE_NAME", "reset"], "actual_designator" : ["SIMPLE_NAME", "reset"]}
......
931 931
            ]}
932 932
          ]}
933 933
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
934
          "name" : ["IDENTIFIER", "assert_unit"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "assert_uut"]]], "archi_name" : ["IDENTIFIER", "rtl"], "port_map" : [{
934
          "name" : ["IDENTIFIER", "assert_unit"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "assert_uut"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "rtl"], "port_map" : [{
935 935
            "formal_name" : ["SIMPLE_NAME", "clock"], "actual_designator" : ["SIMPLE_NAME", "clock"]}
936 936
          , {
937 937
            "formal_name" : ["SIMPLE_NAME", "reset"], "actual_designator" : ["SIMPLE_NAME", "reset"]}
......
961 961
            "formal_name" : ["SIMPLE_NAME", "n_error"], "actual_designator" : ["SIMPLE_NAME", "n_error_s"]}
962 962
          ]}
963 963
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
964
          "name" : ["IDENTIFIER", "prog_unit"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "prog"]]], "archi_name" : ["IDENTIFIER", "rtl"], "port_map" : [{
964
          "name" : ["IDENTIFIER", "prog_unit"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "prog"]]], "inst_unit_type" : "entity", "archi_name" : ["IDENTIFIER", "rtl"], "port_map" : [{
965 965
            "formal_name" : ["SIMPLE_NAME", "clock"], "actual_designator" : ["SIMPLE_NAME", "clock"]}
966 966
          , {
967 967
            "formal_name" : ["SIMPLE_NAME", "reset"], "actual_designator" : ["SIMPLE_NAME", "reset"]}

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