Project

General

Profile

« Previous | Next » 

Revision ddabd63e

Added by Arnaud Dieumegard over 3 years ago

Updated tests for lustrei vhdl import

View differences:

vhdl_json/vhdl_files/2-exportOK/cnes_guidelines/rule/data/STD_05700_bad.json
55 55
            }
56 56
          ]}
57 57
        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
58
          "name" : ["IDENTIFIER", "DFF_En"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "port_map" : [{
58
          "name" : ["IDENTIFIER", "DFF_En"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "inst_unit_type" : "component", "port_map" : [{
59 59
            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "i_Clock"]}
60 60
          , {
61 61
            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}

Also available in: Unified diff