Project

General

Profile

« Previous | Next » 

Revision ddabd63e

Added by Arnaud Dieumegard over 3 years ago

Updated tests for lustrei vhdl import

View differences:

vhdl_json/vhdl_files/2-exportOK/Plasma/vhdl/General/BiDirFifoBuffer.json
711 711
            ]}
712 712
          ]}
713 713
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
714
          "name" : ["IDENTIFIER", "TX_FIFO"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fifo2048x8"]]], "port_map" : [{
714
          "name" : ["IDENTIFIER", "TX_FIFO"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fifo2048x8"]]], "inst_unit_type" : "entity", "port_map" : [{
715 715
            "formal_name" : ["SIMPLE_NAME", "rst"], "actual_designator" : ["SIMPLE_NAME", "cpu_tx_reset"]}
716 716
          , {
717 717
            "formal_name" : ["SIMPLE_NAME", "wr_clk"], "actual_designator" : ["SIMPLE_NAME", "clk_cpu"]}
......
731 731
            "formal_name" : ["SIMPLE_NAME", "empty"], "actual_designator" : ["SIMPLE_NAME", "tx_fifo_empty"]}
732 732
          ]}
733 733
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
734
          "name" : ["IDENTIFIER", "RX_FIFO"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fifo2048x8"]]], "port_map" : [{
734
          "name" : ["IDENTIFIER", "RX_FIFO"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fifo2048x8"]]], "inst_unit_type" : "entity", "port_map" : [{
735 735
            "formal_name" : ["SIMPLE_NAME", "rst"], "actual_designator" : ["SIMPLE_NAME", "cpu_rx_reset"]}
736 736
          , {
737 737
            "formal_name" : ["SIMPLE_NAME", "wr_clk"], "actual_designator" : ["SIMPLE_NAME", "clk_io"]}

Also available in: Unified diff