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Revision ddabd63e

Added by Arnaud Dieumegard over 3 years ago

Updated tests for lustrei vhdl import

View differences:

vhdl_json/vhdl_files/2-exportOK/Plasma/C/PlasmaBootLoader/ram_xilinx.json
109 109
    , {
110 110
      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
111 111
        "name" : ["IDENTIFIER", "logic"], "entity" : ["IDENTIFIER", "ram_PlasmaBootLoader"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
112
          "name" : ["IDENTIFIER", "RAMB16_S9_inst0"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "generic_map" : [{
112
          "name" : ["IDENTIFIER", "RAMB16_S9_inst0"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "inst_unit_type" : "component", "generic_map" : [{
113 113
            "formal_name" : ["SIMPLE_NAME", "INIT_00"], "actual_expr" : ["EXPRESSION", {
114 114
              "args" : [["EXPRESSION", {
115 115
                "args" : [["EXPRESSION", {
......
1005 1005
            ]}
1006 1006
          ]}
1007 1007
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
1008
          "name" : ["IDENTIFIER", "RAMB16_S9_inst1"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "generic_map" : [{
1008
          "name" : ["IDENTIFIER", "RAMB16_S9_inst1"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "inst_unit_type" : "component", "generic_map" : [{
1009 1009
            "formal_name" : ["SIMPLE_NAME", "INIT_00"], "actual_expr" : ["EXPRESSION", {
1010 1010
              "args" : [["EXPRESSION", {
1011 1011
                "args" : [["EXPRESSION", {
......
1901 1901
            ]}
1902 1902
          ]}
1903 1903
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
1904
          "name" : ["IDENTIFIER", "RAMB16_S9_inst2"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "generic_map" : [{
1904
          "name" : ["IDENTIFIER", "RAMB16_S9_inst2"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "inst_unit_type" : "component", "generic_map" : [{
1905 1905
            "formal_name" : ["SIMPLE_NAME", "INIT_00"], "actual_expr" : ["EXPRESSION", {
1906 1906
              "args" : [["EXPRESSION", {
1907 1907
                "args" : [["EXPRESSION", {
......
2797 2797
            ]}
2798 2798
          ]}
2799 2799
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
2800
          "name" : ["IDENTIFIER", "RAMB16_S9_inst3"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "generic_map" : [{
2800
          "name" : ["IDENTIFIER", "RAMB16_S9_inst3"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "inst_unit_type" : "component", "generic_map" : [{
2801 2801
            "formal_name" : ["SIMPLE_NAME", "INIT_00"], "actual_expr" : ["EXPRESSION", {
2802 2802
              "args" : [["EXPRESSION", {
2803 2803
                "args" : [["EXPRESSION", {
vhdl_json/vhdl_files/2-exportOK/Plasma/C/PlasmaDataAcquisition/ram_PlasmaDataAcquisition.json
109 109
    , {
110 110
      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
111 111
        "name" : ["IDENTIFIER", "logic"], "entity" : ["IDENTIFIER", "ram_Program"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
112
          "name" : ["IDENTIFIER", "RAMB16_S9_inst0"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "generic_map" : [{
112
          "name" : ["IDENTIFIER", "RAMB16_S9_inst0"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "inst_unit_type" : "component", "generic_map" : [{
113 113
            "formal_name" : ["SIMPLE_NAME", "INIT_00"], "actual_expr" : ["EXPRESSION", {
114 114
              "args" : [["EXPRESSION", {
115 115
                "args" : [["EXPRESSION", {
......
1005 1005
            ]}
1006 1006
          ]}
1007 1007
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
1008
          "name" : ["IDENTIFIER", "RAMB16_S9_inst1"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "generic_map" : [{
1008
          "name" : ["IDENTIFIER", "RAMB16_S9_inst1"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "inst_unit_type" : "component", "generic_map" : [{
1009 1009
            "formal_name" : ["SIMPLE_NAME", "INIT_00"], "actual_expr" : ["EXPRESSION", {
1010 1010
              "args" : [["EXPRESSION", {
1011 1011
                "args" : [["EXPRESSION", {
......
1901 1901
            ]}
1902 1902
          ]}
1903 1903
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
1904
          "name" : ["IDENTIFIER", "RAMB16_S9_inst2"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "generic_map" : [{
1904
          "name" : ["IDENTIFIER", "RAMB16_S9_inst2"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "inst_unit_type" : "component", "generic_map" : [{
1905 1905
            "formal_name" : ["SIMPLE_NAME", "INIT_00"], "actual_expr" : ["EXPRESSION", {
1906 1906
              "args" : [["EXPRESSION", {
1907 1907
                "args" : [["EXPRESSION", {
......
2797 2797
            ]}
2798 2798
          ]}
2799 2799
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
2800
          "name" : ["IDENTIFIER", "RAMB16_S9_inst3"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "generic_map" : [{
2800
          "name" : ["IDENTIFIER", "RAMB16_S9_inst3"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "inst_unit_type" : "component", "generic_map" : [{
2801 2801
            "formal_name" : ["SIMPLE_NAME", "INIT_00"], "actual_expr" : ["EXPRESSION", {
2802 2802
              "args" : [["EXPRESSION", {
2803 2803
                "args" : [["EXPRESSION", {
vhdl_json/vhdl_files/2-exportOK/Plasma/Tools/lib/ram_xilinx.json
109 109
    , {
110 110
      "contexts" : [], "library" : ["ARCHITECTURE_BODY", {
111 111
        "name" : ["IDENTIFIER", "logic"], "entity" : ["IDENTIFIER", "ram_Program"], "ARCHITECTURE_DECLARATIVE_PART" : [], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
112
          "name" : ["IDENTIFIER", "RAMB16_S9_inst0"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "generic_map" : [{
112
          "name" : ["IDENTIFIER", "RAMB16_S9_inst0"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "inst_unit_type" : "component", "generic_map" : [{
113 113
            "formal_name" : ["SIMPLE_NAME", "INIT_00"], "actual_expr" : ["EXPRESSION", {
114 114
              "args" : [["EXPRESSION", {
115 115
                "args" : [["EXPRESSION", {
......
1005 1005
            ]}
1006 1006
          ]}
1007 1007
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
1008
          "name" : ["IDENTIFIER", "RAMB16_S9_inst1"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "generic_map" : [{
1008
          "name" : ["IDENTIFIER", "RAMB16_S9_inst1"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "inst_unit_type" : "component", "generic_map" : [{
1009 1009
            "formal_name" : ["SIMPLE_NAME", "INIT_00"], "actual_expr" : ["EXPRESSION", {
1010 1010
              "args" : [["EXPRESSION", {
1011 1011
                "args" : [["EXPRESSION", {
......
1901 1901
            ]}
1902 1902
          ]}
1903 1903
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
1904
          "name" : ["IDENTIFIER", "RAMB16_S9_inst2"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "generic_map" : [{
1904
          "name" : ["IDENTIFIER", "RAMB16_S9_inst2"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "inst_unit_type" : "component", "generic_map" : [{
1905 1905
            "formal_name" : ["SIMPLE_NAME", "INIT_00"], "actual_expr" : ["EXPRESSION", {
1906 1906
              "args" : [["EXPRESSION", {
1907 1907
                "args" : [["EXPRESSION", {
......
2797 2797
            ]}
2798 2798
          ]}
2799 2799
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
2800
          "name" : ["IDENTIFIER", "RAMB16_S9_inst3"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "generic_map" : [{
2800
          "name" : ["IDENTIFIER", "RAMB16_S9_inst3"], "inst_unit" : ["SIMPLE_NAME", "RAMB16_S9"], "inst_unit_type" : "component", "generic_map" : [{
2801 2801
            "formal_name" : ["SIMPLE_NAME", "INIT_00"], "actual_expr" : ["EXPRESSION", {
2802 2802
              "args" : [["EXPRESSION", {
2803 2803
                "args" : [["EXPRESSION", {
vhdl_json/vhdl_files/2-exportOK/Plasma/vhdl/AtlysDDR/atlys_ddr2.json
4181 4181
            ]}
4182 4182
          ]}
4183 4183
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
4184
          "name" : ["IDENTIFIER", "memc3_infrastructure_inst"], "inst_unit" : ["SIMPLE_NAME", "memc3_infrastructure"], "generic_map" : [{
4184
          "name" : ["IDENTIFIER", "memc3_infrastructure_inst"], "inst_unit" : ["SIMPLE_NAME", "memc3_infrastructure"], "inst_unit_type" : "component", "generic_map" : [{
4185 4185
            "formal_name" : ["SIMPLE_NAME", "C_RST_ACT_LOW"], "actual_designator" : ["SIMPLE_NAME", "C3_RST_ACT_LOW"]}
4186 4186
          , {
4187 4187
            "formal_name" : ["SIMPLE_NAME", "C_INPUT_CLK_TYPE"], "actual_designator" : ["SIMPLE_NAME", "C3_INPUT_CLK_TYPE"]}
......
4231 4231
            "formal_name" : ["SIMPLE_NAME", "clk4"], "actual_designator" : ["SIMPLE_NAME", "c3_clk4"]}
4232 4232
          ]}
4233 4233
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
4234
          "name" : ["IDENTIFIER", "memc3_wrapper_inst"], "inst_unit" : ["SIMPLE_NAME", "memc3_wrapper"], "generic_map" : [{
4234
          "name" : ["IDENTIFIER", "memc3_wrapper_inst"], "inst_unit" : ["SIMPLE_NAME", "memc3_wrapper"], "inst_unit_type" : "component", "generic_map" : [{
4235 4235
            "formal_name" : ["SIMPLE_NAME", "C_MEMCLK_PERIOD"], "actual_designator" : ["SIMPLE_NAME", "C3_MEMCLK_PERIOD"]}
4236 4236
          , {
4237 4237
            "formal_name" : ["SIMPLE_NAME", "C_CALIB_SOFT_IP"], "actual_designator" : ["SIMPLE_NAME", "C3_CALIB_SOFT_IP"]}
vhdl_json/vhdl_files/2-exportOK/Plasma/vhdl/AtlysDDR/atlys_ddr2_sim_model.json
1385 1385
            ]}
1386 1386
          ]]}
1387 1387
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
1388
          "name" : ["IDENTIFIER", "p0_WriteFifo"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fifo64x8N"]]], "generic_map" : [{
1388
          "name" : ["IDENTIFIER", "p0_WriteFifo"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fifo64x8N"]]], "inst_unit_type" : "entity", "generic_map" : [{
1389 1389
            "formal_name" : ["SIMPLE_NAME", "N"], "actual_expr" : ["EXPRESSION", {
1390 1390
              "args" : [["EXPRESSION", {
1391 1391
                "args" : [["EXPRESSION", {
......
1419 1419
            "formal_name" : ["SIMPLE_NAME", "wr_data_count"], "actual_designator" : ["SIMPLE_NAME", "wf0_cnt"]}
1420 1420
          ]}
1421 1421
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
1422
          "name" : ["IDENTIFIER", "p1_WriteFifo"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fifo64x8N"]]], "generic_map" : [{
1422
          "name" : ["IDENTIFIER", "p1_WriteFifo"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fifo64x8N"]]], "inst_unit_type" : "entity", "generic_map" : [{
1423 1423
            "formal_name" : ["SIMPLE_NAME", "N"], "actual_expr" : ["EXPRESSION", {
1424 1424
              "args" : [["EXPRESSION", {
1425 1425
                "args" : [["EXPRESSION", {
......
1453 1453
            "formal_name" : ["SIMPLE_NAME", "wr_data_count"], "actual_designator" : ["SIMPLE_NAME", "wf1_cnt"]}
1454 1454
          ]}
1455 1455
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
1456
          "name" : ["IDENTIFIER", "p0_ReadFifo"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fifo64x8N"]]], "generic_map" : [{
1456
          "name" : ["IDENTIFIER", "p0_ReadFifo"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fifo64x8N"]]], "inst_unit_type" : "entity", "generic_map" : [{
1457 1457
            "formal_name" : ["SIMPLE_NAME", "N"], "actual_expr" : ["EXPRESSION", {
1458 1458
              "args" : [["EXPRESSION", {
1459 1459
                "args" : [["EXPRESSION", {
......
1515 1515
            ]}
1516 1516
          ]}
1517 1517
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
1518
          "name" : ["IDENTIFIER", "p1_ReadFifo"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fifo64x8N"]]], "generic_map" : [{
1518
          "name" : ["IDENTIFIER", "p1_ReadFifo"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fifo64x8N"]]], "inst_unit_type" : "entity", "generic_map" : [{
1519 1519
            "formal_name" : ["SIMPLE_NAME", "N"], "actual_expr" : ["EXPRESSION", {
1520 1520
              "args" : [["EXPRESSION", {
1521 1521
                "args" : [["EXPRESSION", {
......
3607 3607
            ]}
3608 3608
          ]}
3609 3609
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
3610
          "name" : ["IDENTIFIER", "ram"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "dualRamMx8N"]]], "generic_map" : [{
3610
          "name" : ["IDENTIFIER", "ram"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "dualRamMx8N"]]], "inst_unit_type" : "entity", "generic_map" : [{
3611 3611
            "formal_name" : ["SIMPLE_NAME", "N"], "actual_expr" : ["EXPRESSION", {
3612 3612
              "args" : [["EXPRESSION", {
3613 3613
                "args" : [["EXPRESSION", {
vhdl_json/vhdl_files/2-exportOK/Plasma/vhdl/AtlysDDR/ddr2_cache.json
2809 2809
            ]}
2810 2810
          ]}
2811 2811
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
2812
          "name" : ["IDENTIFIER", "u1_cache"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "dualRamMx8N"]]], "generic_map" : [{
2812
          "name" : ["IDENTIFIER", "u1_cache"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "dualRamMx8N"]]], "inst_unit_type" : "entity", "generic_map" : [{
2813 2813
            "formal_name" : ["SIMPLE_NAME", "N"], "actual_expr" : ["EXPRESSION", {
2814 2814
              "args" : [["EXPRESSION", {
2815 2815
                "args" : [["EXPRESSION", {
......
2863 2863
            "formal_name" : ["SIMPLE_NAME", "doutb"], "actual_designator" : ["SIMPLE_NAME", "open"]}
2864 2864
          ]}
2865 2865
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
2866
          "name" : ["IDENTIFIER", "u2_cacheTable"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "cache_table"]]], "generic_map" : [{
2866
          "name" : ["IDENTIFIER", "u2_cacheTable"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "cache_table"]]], "inst_unit_type" : "entity", "generic_map" : [{
2867 2867
            "formal_name" : ["SIMPLE_NAME", "TABLE_WIDTH"], "actual_designator" : ["SIMPLE_NAME", "TABLE_WIDTH"]}
2868 2868
          , {
2869 2869
            "formal_name" : ["SIMPLE_NAME", "ADDR_WIDTH"], "actual_designator" : ["SIMPLE_NAME", "CACHE_WIDTH"]}
vhdl_json/vhdl_files/2-exportOK/Plasma/vhdl/Ethernet/EthernetRx_old.json
3281 3281
            ]}
3282 3282
          ]}
3283 3283
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
3284
          "name" : ["IDENTIFIER", "RAM"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "dualRam8kx8_2kx32"]]], "port_map" : [{
3284
          "name" : ["IDENTIFIER", "RAM"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "dualRam8kx8_2kx32"]]], "inst_unit_type" : "entity", "port_map" : [{
3285 3285
            "formal_name" : ["SIMPLE_NAME", "clka"], "actual_designator" : ["SIMPLE_NAME", "ethernetRXCLK"]}
3286 3286
          , {
3287 3287
            "formal_name" : ["SIMPLE_NAME", "wea"], "actual_designator" : ["SIMPLE_NAME", "ramWea"]}
vhdl_json/vhdl_files/2-exportOK/Plasma/vhdl/Ethernet/EthernetTop.json
2339 2339
            ]]}
2340 2340
          ]]}
2341 2341
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
2342
          "name" : ["IDENTIFIER", "RXD_IF"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "EthernetRx"]]], "port_map" : [{
2342
          "name" : ["IDENTIFIER", "RXD_IF"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "EthernetRx"]]], "inst_unit_type" : "entity", "port_map" : [{
2343 2343
            "formal_name" : ["SIMPLE_NAME", "clk_50"], "actual_designator" : ["SIMPLE_NAME", "clk"]}
2344 2344
          , {
2345 2345
            "formal_name" : ["SIMPLE_NAME", "reset_n"], "actual_designator" : ["SIMPLE_NAME", "reset_n"]}
......
2373 2373
            "formal_name" : ["SIMPLE_NAME", "MacLow"], "actual_designator" : ["SIMPLE_NAME", "MacLow"]}
2374 2374
          ]}
2375 2375
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
2376
          "name" : ["IDENTIFIER", "TXD_IF"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "EthernetTx"]]], "port_map" : [{
2376
          "name" : ["IDENTIFIER", "TXD_IF"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "EthernetTx"]]], "inst_unit_type" : "entity", "port_map" : [{
2377 2377
            "formal_name" : ["SIMPLE_NAME", "clk_50"], "actual_designator" : ["SIMPLE_NAME", "clk"]}
2378 2378
          , {
2379 2379
            "formal_name" : ["SIMPLE_NAME", "clk_125"], "actual_designator" : ["SIMPLE_NAME", "clk_125"]}
......
2409 2409
            "formal_name" : ["SIMPLE_NAME", "MacLow"], "actual_designator" : ["SIMPLE_NAME", "MacLow"]}
2410 2410
          ]}
2411 2411
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
2412
          "name" : ["IDENTIFIER", "MDIO_IF"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "EthernetMDIO"]]], "port_map" : [{
2412
          "name" : ["IDENTIFIER", "MDIO_IF"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "EthernetMDIO"]]], "inst_unit_type" : "entity", "port_map" : [{
2413 2413
            "formal_name" : ["SIMPLE_NAME", "clk_50"], "actual_designator" : ["SIMPLE_NAME", "clk"]}
2414 2414
          , {
2415 2415
            "formal_name" : ["SIMPLE_NAME", "reset_n"], "actual_designator" : ["SIMPLE_NAME", "reset_n"]}
vhdl_json/vhdl_files/2-exportOK/Plasma/vhdl/General/BiDirFifoBuffer.json
711 711
            ]}
712 712
          ]}
713 713
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
714
          "name" : ["IDENTIFIER", "TX_FIFO"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fifo2048x8"]]], "port_map" : [{
714
          "name" : ["IDENTIFIER", "TX_FIFO"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fifo2048x8"]]], "inst_unit_type" : "entity", "port_map" : [{
715 715
            "formal_name" : ["SIMPLE_NAME", "rst"], "actual_designator" : ["SIMPLE_NAME", "cpu_tx_reset"]}
716 716
          , {
717 717
            "formal_name" : ["SIMPLE_NAME", "wr_clk"], "actual_designator" : ["SIMPLE_NAME", "clk_cpu"]}
......
731 731
            "formal_name" : ["SIMPLE_NAME", "empty"], "actual_designator" : ["SIMPLE_NAME", "tx_fifo_empty"]}
732 732
          ]}
733 733
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
734
          "name" : ["IDENTIFIER", "RX_FIFO"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fifo2048x8"]]], "port_map" : [{
734
          "name" : ["IDENTIFIER", "RX_FIFO"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "fifo2048x8"]]], "inst_unit_type" : "entity", "port_map" : [{
735 735
            "formal_name" : ["SIMPLE_NAME", "rst"], "actual_designator" : ["SIMPLE_NAME", "cpu_rx_reset"]}
736 736
          , {
737 737
            "formal_name" : ["SIMPLE_NAME", "wr_clk"], "actual_designator" : ["SIMPLE_NAME", "clk_io"]}
vhdl_json/vhdl_files/2-exportOK/Plasma/vhdl/General/uartCore.json
767 767
            }
768 768
          ]}
769 769
        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
770
          "name" : ["IDENTIFIER", "u1_rx_in"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "InputPort"]]], "generic_map" : [{
770
          "name" : ["IDENTIFIER", "u1_rx_in"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "InputPort"]]], "inst_unit_type" : "entity", "generic_map" : [{
771 771
            "formal_name" : ["SIMPLE_NAME", "W"], "actual_expr" : ["EXPRESSION", {
772 772
              "args" : [["EXPRESSION", {
773 773
                "args" : [["EXPRESSION", {
vhdl_json/vhdl_files/2-exportOK/Plasma/vhdl/Testbenches/UartFileReader.json
767 767
            ]}
768 768
          ]}
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......
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127 127
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128 128
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129 129
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57 57
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58 58
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59 59
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60
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61 61
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62 62
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63 63
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55 55
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56 56
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60 60
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61 61
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36 36
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37 37
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40 40
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41 41
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21 21
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28 28
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29 29
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71 71
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72 72
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76 76
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77 77
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......
81 81
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82 82
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83 83
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......
81 81
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82 82
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30 30
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31 31
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35 35
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129 129
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133 133
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134 134
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135 135
            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}
vhdl_json/vhdl_files/2-exportOK/cnes_guidelines/rule/data/STD_03900_good.json
117 117
            }
118 118
          ]}
119 119
        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
120
          "name" : ["IDENTIFIER", "Counter"], "inst_unit" : ["SIMPLE_NAME", "Counter"], "port_map" : [{
120
          "name" : ["IDENTIFIER", "Counter"], "inst_unit" : ["SIMPLE_NAME", "Counter"], "inst_unit_type" : "component", "port_map" : [{
121 121
            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "i_Clock"]}
122 122
          , {
123 123
            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}
vhdl_json/vhdl_files/2-exportOK/cnes_guidelines/rule/data/STD_04000_bad.json
117 117
            }
118 118
          ]}
119 119
        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
120
          "name" : ["IDENTIFIER", "Counter"], "inst_unit" : ["SIMPLE_NAME", "Counter"], "port_map" : [{
120
          "name" : ["IDENTIFIER", "Counter"], "inst_unit" : ["SIMPLE_NAME", "Counter"], "inst_unit_type" : "component", "port_map" : [{
121 121
            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "i_Clock"]}
122 122
          , {
123 123
            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}
vhdl_json/vhdl_files/2-exportOK/cnes_guidelines/rule/data/STD_04000_good.json
117 117
            }
118 118
          ]}
119 119
        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
120
          "name" : ["IDENTIFIER", "Counter"], "inst_unit" : ["SIMPLE_NAME", "Counter"], "port_map" : [{
120
          "name" : ["IDENTIFIER", "Counter"], "inst_unit" : ["SIMPLE_NAME", "Counter"], "inst_unit_type" : "component", "port_map" : [{
121 121
            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "i_Clock"]}
122 122
          , {
123 123
            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}
vhdl_json/vhdl_files/2-exportOK/cnes_guidelines/rule/data/STD_04500_bad.json
103 103
            ]}
104 104
          ]}
105 105
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
106
          "name" : ["IDENTIFIER", "DFF1"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "port_map" : [{
106
          "name" : ["IDENTIFIER", "DFF1"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "inst_unit_type" : "component", "port_map" : [{
107 107
            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "ClockA"]}
108 108
          , {
109 109
            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}
......
115 115
            "formal_name" : ["SIMPLE_NAME", "o_Q_n"], "actual_designator" : ["SIMPLE_NAME", "open"]}
116 116
          ]}
117 117
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
118
          "name" : ["IDENTIFIER", "DFF2"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "port_map" : [{
118
          "name" : ["IDENTIFIER", "DFF2"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "inst_unit_type" : "component", "port_map" : [{
119 119
            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "ClockB"]}
120 120
          , {
121 121
            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}
......
127 127
            "formal_name" : ["SIMPLE_NAME", "o_Q_n"], "actual_designator" : ["SIMPLE_NAME", "open"]}
128 128
          ]}
129 129
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
130
          "name" : ["IDENTIFIER", "DFF3"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "port_map" : [{
130
          "name" : ["IDENTIFIER", "DFF3"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "inst_unit_type" : "component", "port_map" : [{
131 131
            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "ClockC"]}
132 132
          , {
133 133
            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}
vhdl_json/vhdl_files/2-exportOK/cnes_guidelines/rule/data/STD_04500_good.json
43 43
            }
44 44
          ]}
45 45
        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
46
          "name" : ["IDENTIFIER", "DFF1"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "port_map" : [{
46
          "name" : ["IDENTIFIER", "DFF1"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "inst_unit_type" : "component", "port_map" : [{
47 47
            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "i_Clock"]}
48 48
          , {
49 49
            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}
......
55 55
            "formal_name" : ["SIMPLE_NAME", "o_Q_n"], "actual_designator" : ["SIMPLE_NAME", "open"]}
56 56
          ]}
57 57
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
58
          "name" : ["IDENTIFIER", "DFF2"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "port_map" : [{
58
          "name" : ["IDENTIFIER", "DFF2"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "inst_unit_type" : "component", "port_map" : [{
59 59
            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "i_Clock"]}
60 60
          , {
61 61
            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}
......
67 67
            "formal_name" : ["SIMPLE_NAME", "o_Q_n"], "actual_designator" : ["SIMPLE_NAME", "open"]}
68 68
          ]}
69 69
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
70
          "name" : ["IDENTIFIER", "DFF3"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "port_map" : [{
70
          "name" : ["IDENTIFIER", "DFF3"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "inst_unit_type" : "component", "port_map" : [{
71 71
            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "i_Clock"]}
72 72
          , {
73 73
            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}
vhdl_json/vhdl_files/2-exportOK/cnes_guidelines/rule/data/STD_05600_bad.json
59 59
            ]}
60 60
          ]}
61 61
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
62
          "name" : ["IDENTIFIER", "Mux1"], "inst_unit" : ["SIMPLE_NAME", "Mux"], "port_map" : [{
62
          "name" : ["IDENTIFIER", "Mux1"], "inst_unit" : ["SIMPLE_NAME", "Mux"], "inst_unit_type" : "component", "port_map" : [{
63 63
            "formal_name" : ["SIMPLE_NAME", "i_A"], "actual_designator" : ["SIMPLE_NAME", "i_A"]}
64 64
          , {
65 65
            "formal_name" : ["SIMPLE_NAME", "i_B"], "actual_designator" : ["SIMPLE_NAME", "i_B"]}
vhdl_json/vhdl_files/2-exportOK/cnes_guidelines/rule/data/STD_05600_good.json
73 73
            ]}
74 74
          ]}
75 75
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
76
          "name" : ["IDENTIFIER", "DFF"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "port_map" : [{
76
          "name" : ["IDENTIFIER", "DFF"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "inst_unit_type" : "component", "port_map" : [{
77 77
            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "i_Clock"]}
78 78
          , {
79 79
            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}
......
83 83
            "formal_name" : ["SIMPLE_NAME", "o_Q"], "actual_designator" : ["SIMPLE_NAME", "Mux_Sel_r"]}
84 84
          ]}
85 85
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
86
          "name" : ["IDENTIFIER", "Mux1"], "inst_unit" : ["SIMPLE_NAME", "Mux"], "port_map" : [{
86
          "name" : ["IDENTIFIER", "Mux1"], "inst_unit" : ["SIMPLE_NAME", "Mux"], "inst_unit_type" : "component", "port_map" : [{
87 87
            "formal_name" : ["SIMPLE_NAME", "i_A"], "actual_designator" : ["SIMPLE_NAME", "i_A"]}
88 88
          , {
89 89
            "formal_name" : ["SIMPLE_NAME", "i_B"], "actual_designator" : ["SIMPLE_NAME", "i_B"]}
vhdl_json/vhdl_files/2-exportOK/cnes_guidelines/rule/data/STD_05700_bad.json
55 55
            }
56 56
          ]}
57 57
        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
58
          "name" : ["IDENTIFIER", "DFF_En"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "port_map" : [{
58
          "name" : ["IDENTIFIER", "DFF_En"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "inst_unit_type" : "component", "port_map" : [{
59 59
            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "i_Clock"]}
60 60
          , {
61 61
            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}
vhdl_json/vhdl_files/2-exportOK/cnes_guidelines/rule/data/STD_05700_good.json
49 49
            }
50 50
          ]}
51 51
        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
52
          "name" : ["IDENTIFIER", "DFF_En"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "port_map" : [{
52
          "name" : ["IDENTIFIER", "DFF_En"], "inst_unit" : ["SIMPLE_NAME", "DFlipFlop"], "inst_unit_type" : "component", "port_map" : [{
53 53
            "formal_name" : ["SIMPLE_NAME", "i_Clock"], "actual_designator" : ["SIMPLE_NAME", "i_Clock"]}
54 54
          , {
55 55
            "formal_name" : ["SIMPLE_NAME", "i_Reset_n"], "actual_designator" : ["SIMPLE_NAME", "i_Reset_n"]}
vhdl_json/vhdl_files/2-exportOK/cnes_guidelines/rule/data/best-chronometer-ever/src/best_chronometer_ever.json
923 923
            ]}
924 924
          ]}
925 925
        ], "ARCHITECTURE_STATEMENT_PART" : [["COMPONENT_INSTANTIATION_STATEMENT", {
926
          "name" : ["IDENTIFIER", "START_BP_SYNCHRONIZER"], "inst_unit" : ["SIMPLE_NAME", "crossdomain_sync"], "port_map" : [{
926
          "name" : ["IDENTIFIER", "START_BP_SYNCHRONIZER"], "inst_unit" : ["SIMPLE_NAME", "crossdomain_sync"], "inst_unit_type" : "component", "port_map" : [{
927 927
            "formal_name" : ["SIMPLE_NAME", "i_clock"], "actual_designator" : ["SIMPLE_NAME", "i_clock"]}
928 928
          , {
929 929
            "formal_name" : ["SIMPLE_NAME", "i_reset"], "actual_designator" : ["SIMPLE_NAME", "i_reset"]}
......
933 933
            "formal_name" : ["SIMPLE_NAME", "o_signal"], "actual_designator" : ["SIMPLE_NAME", "synced_start_bp"]}
934 934
          ]}
935 935
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
936
          "name" : ["IDENTIFIER", "RAZ_BP_SYNCHRONIZER"], "inst_unit" : ["SIMPLE_NAME", "crossdomain_sync"], "port_map" : [{
936
          "name" : ["IDENTIFIER", "RAZ_BP_SYNCHRONIZER"], "inst_unit" : ["SIMPLE_NAME", "crossdomain_sync"], "inst_unit_type" : "component", "port_map" : [{
937 937
            "formal_name" : ["SIMPLE_NAME", "i_clock"], "actual_designator" : ["SIMPLE_NAME", "i_clock"]}
938 938
          , {
939 939
            "formal_name" : ["SIMPLE_NAME", "i_reset"], "actual_designator" : ["SIMPLE_NAME", "i_reset"]}
......
943 943
            "formal_name" : ["SIMPLE_NAME", "o_signal"], "actual_designator" : ["SIMPLE_NAME", "synced_raz_bp"]}
944 944
          ]}
945 945
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
946
          "name" : ["IDENTIFIER", "CNTSCD_TM"], "inst_unit" : ["SIMPLE_NAME", "centisecond_timer"], "port_map" : [{
946
          "name" : ["IDENTIFIER", "CNTSCD_TM"], "inst_unit" : ["SIMPLE_NAME", "centisecond_timer"], "inst_unit_type" : "component", "port_map" : [{
947 947
            "formal_name" : ["SIMPLE_NAME", "i_clock"], "actual_designator" : ["SIMPLE_NAME", "i_clock"]}
948 948
          , {
949 949
            "formal_name" : ["SIMPLE_NAME", "i_reset"], "actual_designator" : ["SIMPLE_NAME", "i_reset"]}
......
955 955
            "formal_name" : ["SIMPLE_NAME", "o_new_centisecond"], "actual_designator" : ["SIMPLE_NAME", "new_centisecond"]}
956 956
          ]}
957 957
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
958
          "name" : ["IDENTIFIER", "DSPLY_MGR"], "inst_unit" : ["SIMPLE_NAME", "display_manager"], "port_map" : [{
958
          "name" : ["IDENTIFIER", "DSPLY_MGR"], "inst_unit" : ["SIMPLE_NAME", "display_manager"], "inst_unit_type" : "component", "port_map" : [{
959 959
            "formal_name" : ["SIMPLE_NAME", "i_clock"], "actual_designator" : ["SIMPLE_NAME", "i_clock"]}
960 960
          , {
961 961
            "formal_name" : ["SIMPLE_NAME", "i_reset"], "actual_designator" : ["SIMPLE_NAME", "i_reset"]}
......
973 973
            "formal_name" : ["SIMPLE_NAME", "o_an"], "actual_designator" : ["SIMPLE_NAME", "o_an"]}
974 974
          ]}
975 975
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
976
          "name" : ["IDENTIFIER", "DSPLY_TRSLTR"], "inst_unit" : ["SIMPLE_NAME", "numeral_to_display"], "port_map" : [{
976
          "name" : ["IDENTIFIER", "DSPLY_TRSLTR"], "inst_unit" : ["SIMPLE_NAME", "numeral_to_display"], "inst_unit_type" : "component", "port_map" : [{
977 977
            "formal_name" : ["SIMPLE_NAME", "i_numeral_time"], "actual_designator" : ["SIMPLE_NAME", "numeral_display"]}
978 978
          , {
979 979
            "formal_name" : ["SIMPLE_NAME", "o_display"], "actual_designator" : ["SIMPLE_NAME", "o_display"]}
980 980
          ]}
981 981
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
982
          "name" : ["IDENTIFIER", "TM_WZRD"], "inst_unit" : ["SIMPLE_NAME", "time_wizard"], "port_map" : [{
982
          "name" : ["IDENTIFIER", "TM_WZRD"], "inst_unit" : ["SIMPLE_NAME", "time_wizard"], "inst_unit_type" : "component", "port_map" : [{
983 983
            "formal_name" : ["SIMPLE_NAME", "i_clock"], "actual_designator" : ["SIMPLE_NAME", "i_clock"]}
984 984
          , {
985 985
            "formal_name" : ["SIMPLE_NAME", "i_reset"], "actual_designator" : ["SIMPLE_NAME", "i_reset"]}
......
999 999
            "formal_name" : ["SIMPLE_NAME", "o_curr_1000_time"], "actual_designator" : ["SIMPLE_NAME", "curr_1000_time"]}
1000 1000
          ]}
1001 1001
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
1002
          "name" : ["IDENTIFIER", "USR_HNDLR"], "inst_unit" : ["SIMPLE_NAME", "user_handler"], "port_map" : [{
1002
          "name" : ["IDENTIFIER", "USR_HNDLR"], "inst_unit" : ["SIMPLE_NAME", "user_handler"], "inst_unit_type" : "component", "port_map" : [{
1003 1003
            "formal_name" : ["SIMPLE_NAME", "i_clock"], "actual_designator" : ["SIMPLE_NAME", "i_clock"]}
1004 1004
          , {
1005 1005
            "formal_name" : ["SIMPLE_NAME", "i_reset"], "actual_designator" : ["SIMPLE_NAME", "i_reset"]}
vhdl_json/vhdl_files/2-exportOK/forth-cpu/ram.json
519 519
            ]}
520 520
          ]}
521 521
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
522
          "name" : ["IDENTIFIER", "mem_addr_16_1_reg"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "reg"]]], "generic_map" : [{
522
          "name" : ["IDENTIFIER", "mem_addr_16_1_reg"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "reg"]]], "inst_unit_type" : "entity", "generic_map" : [{
523 523
            "formal_name" : ["SIMPLE_NAME", "N"], "actual_designator" : ["ATTRIBUTE_NAME", {
524 524
              "id" : ["SIMPLE_NAME", "mem_addr_16_1"], "designator" : ["SIMPLE_NAME", "length"]}
525 525
            ]}
......
535 535
            "formal_name" : ["SIMPLE_NAME", "do"], "actual_designator" : ["SIMPLE_NAME", "mem_addr_low"]}
536 536
          ]}
537 537
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
538
          "name" : ["IDENTIFIER", "mem_addr_26_17_reg"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "reg"]]], "generic_map" : [{
538
          "name" : ["IDENTIFIER", "mem_addr_26_17_reg"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "reg"]]], "inst_unit_type" : "entity", "generic_map" : [{
539 539
            "formal_name" : ["SIMPLE_NAME", "N"], "actual_expr" : ["EXPRESSION", {
540 540
              "args" : [["EXPRESSION", {
541 541
                "args" : [["EXPRESSION", {
......
559 559
            "formal_name" : ["SIMPLE_NAME", "do"], "actual_designator" : ["SIMPLE_NAME", "mem_addr_high"]}
560 560
          ]}
561 561
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
562
          "name" : ["IDENTIFIER", "mem_control_reg"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "reg"]]], "generic_map" : [{
562
          "name" : ["IDENTIFIER", "mem_control_reg"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "reg"]]], "inst_unit_type" : "entity", "generic_map" : [{
563 563
            "formal_name" : ["SIMPLE_NAME", "N"], "actual_expr" : ["EXPRESSION", {
564 564
              "args" : [["EXPRESSION", {
565 565
                "args" : [["EXPRESSION", {
......
583 583
            "formal_name" : ["SIMPLE_NAME", "do"], "actual_designator" : ["SIMPLE_NAME", "mem_control_o"]}
584 584
          ]}
585 585
        ], ["COMPONENT_INSTANTIATION_STATEMENT", {
586
          "name" : ["IDENTIFIER", "mem_data_i_reg"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "reg"]]], "generic_map" : [{
586
          "name" : ["IDENTIFIER", "mem_data_i_reg"], "inst_unit" : ["SELECTED_NAME", [["SIMPLE_NAME", "work"], ["IDENTIFIER", "reg"]]], "inst_unit_type" : "entity", "generic_map" : [{
587 587
            "formal_name" : ["SIMPLE_NAME", "N"], "actual_designator" : ["ATTRIBUTE_NAME", {
588 588
              "id" : ["SIMPLE_NAME", "mem_data_i"], "designator" : ["SIMPLE_NAME", "length"]}
589 589
            ]}
vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/gna/bug040/bit_set_mask.json
541 541
                ]]}
542 542
              ]}
543 543
            ], ["RETURN_STATEMENT", {
544
              }
544
              "expr" : ["EXPRESSION", {
545
                "args" : [["EXPRESSION", {
546
                  "args" : [["EXPRESSION", {
547
                    "args" : [["EXPRESSION", {
548
                      "args" : [["CALL", ["FUNCTION_CALL", {
549
                        "id" : ["SIMPLE_NAME", "to_integer"], "assoc_list" : [{
550
                          "actual_expr" : ["EXPRESSION", {
551
                            "args" : [["EXPRESSION", {
552
                              "args" : [["EXPRESSION", {
553
                                "args" : [["EXPRESSION", {
554
                                  "args" : [["CALL", ["FUNCTION_CALL", {
555
                                    "id" : ["SIMPLE_NAME", "unsigned"], "assoc_list" : [{
556
                                      "actual_designator" : ["SIMPLE_NAME", "V"]}
557
                                    ]}
558
                                  ]]]}
559
                                ]]}
560
                              ]]}
561
                            ]]}
562
                          ]}
563
                        ]}
564
                      ]]]}
565
                    ]]}
566
                  ]]}
567
                ]]}
568
              ]}
545 569
            ]]}
546 570
          ]}
547 571
        , {
......
553 577
                }
554 578
              ], "typeMark" : ["SIMPLE_NAME", "integer"], "isPure" : false}
555 579
            , "stmts" : [["RETURN_STATEMENT", {
556
              }
580
              "expr" : ["EXPRESSION", {
581
                "args" : [["EXPRESSION", {
582
                  "args" : [["EXPRESSION", {
583
                    "args" : [["EXPRESSION", {
584
                      "args" : [["CALL", ["FUNCTION_CALL", {
585
                        "id" : ["SIMPLE_NAME", "to_integer"], "assoc_list" : [{
586
                          "actual_expr" : ["EXPRESSION", {
587
                            "args" : [["EXPRESSION", {
588
                              "args" : [["EXPRESSION", {
589
                                "args" : [["EXPRESSION", {
590
                                  "args" : [["CALL", ["FUNCTION_CALL", {
591
                                    "id" : ["SIMPLE_NAME", "unsigned"], "assoc_list" : [{
592
                                      "actual_designator" : ["SIMPLE_NAME", "V"]}
593
                                    ]}
594
                                  ]]]}
595
                                ]]}
596
                              ]]}
597
                            ]]}
598
                          ]}
599
                        ]}
600
                      ]]]}
601
                    ]]}
602
                  ]]}
603
                ]]}
604
              ]}
557 605
            ]]}
558 606
          ]}
559 607
        ], "ARCHITECTURE_STATEMENT_PART" : [["CONDITIONAL_SIGNAL_ASSIGNMENT", {
vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/gna/bug040/extend_mask.json
397 397
                ]]}
398 398
              ]}
399 399
            ], ["RETURN_STATEMENT", {
400
              }
400
              "expr" : ["EXPRESSION", {
401
                "args" : [["EXPRESSION", {
402
                  "args" : [["EXPRESSION", {
403
                    "args" : [["EXPRESSION", {
404
                      "args" : [["CALL", ["FUNCTION_CALL", {
405
                        "id" : ["SIMPLE_NAME", "to_integer"], "assoc_list" : [{
406
                          "actual_expr" : ["EXPRESSION", {
407
                            "args" : [["EXPRESSION", {
408
                              "args" : [["EXPRESSION", {
409
                                "args" : [["EXPRESSION", {
410
                                  "args" : [["CALL", ["FUNCTION_CALL", {
411
                                    "id" : ["SIMPLE_NAME", "unsigned"], "assoc_list" : [{
412
                                      "actual_designator" : ["SIMPLE_NAME", "V"]}
413
                                    ]}
414
                                  ]]]}
415
                                ]]}
416
                              ]]}
417
                            ]]}
418
                          ]}
419
                        ]}
420
                      ]]]}
421
                    ]]}
422
                  ]]}
423
                ]]}
424
              ]}
401 425
            ]]}
402 426
          ]}
403 427
        , {
......
409 433
                }
410 434
              ], "typeMark" : ["SIMPLE_NAME", "integer"], "isPure" : false}
411 435
            , "stmts" : [["RETURN_STATEMENT", {
412
              }
436
              "expr" : ["EXPRESSION", {
437
                "args" : [["EXPRESSION", {
438
                  "args" : [["EXPRESSION", {
439
                    "args" : [["EXPRESSION", {
440
                      "args" : [["CALL", ["FUNCTION_CALL", {
441
                        "id" : ["SIMPLE_NAME", "to_integer"], "assoc_list" : [{
442
                          "actual_expr" : ["EXPRESSION", {
443
                            "args" : [["EXPRESSION", {
444
                              "args" : [["EXPRESSION", {
445
                                "args" : [["EXPRESSION", {
446
                                  "args" : [["CALL", ["FUNCTION_CALL", {
447
                                    "id" : ["SIMPLE_NAME", "unsigned"], "assoc_list" : [{
448
                                      "actual_designator" : ["SIMPLE_NAME", "V"]}
449
                                    ]}
450
                                  ]]]}
451
                                ]]}
452
                              ]]}
453
                            ]]}
454
                          ]}
455
                        ]}
456
                      ]]]}
457
                    ]]}
458
                  ]]}
459
                ]]}
460
              ]}
413 461
            ]]}
414 462
          ]}
415 463
        ], "ARCHITECTURE_STATEMENT_PART" : [["CONDITIONAL_SIGNAL_ASSIGNMENT", {
vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/gna/bug040/fsm_224.json
7077 7077
                    ]]}
7078 7078
                  ]]}
7079 7079
                ], "if_block" : [["RETURN_STATEMENT", {
7080
                  }
7080
                  "expr" : ["EXPRESSION", {
7081
                    "args" : [["EXPRESSION", {
7082
                      "args" : [["EXPRESSION", {
7083
                        "args" : [["EXPRESSION", {
7084
                          "args" : [["CONSTANT_VALUE", {
7085
                            "value" : ["CST_LITERAL", "'1'"]}
7086
                          ]]}
7087
                        ]]}
7088
                      ]]}
7089
                    ]]}
7090
                  ]}
7081 7091
                ]]}
7082 7092
              ]}
7083 7093
            ], ["RETURN_STATEMENT", {
7084
              }
7094
              "expr" : ["EXPRESSION", {
7095
                "args" : [["EXPRESSION", {
7096
                  "args" : [["EXPRESSION", {
7097
                    "args" : [["EXPRESSION", {
7098
                      "args" : [["CONSTANT_VALUE", {
7099
                        "value" : ["CST_LITERAL", "'0'"]}
7100
                      ]]}
7101
                    ]]}
7102
                  ]]}
7103
                ]]}
7104
              ]}
7085 7105
            ]]}
7086 7106
          ]}
7087 7107
        ], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", {
vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/gna/bug040/huff_make_dhuff_tb_ac_huffcode.json
225 225
                ]]}
226 226
              ]}
227 227
            ], ["RETURN_STATEMENT", {
228
              }
228
              "expr" : ["EXPRESSION", {
229
                "args" : [["EXPRESSION", {
230
                  "args" : [["EXPRESSION", {
231
                    "args" : [["EXPRESSION", {
232
                      "args" : [["CALL", ["FUNCTION_CALL", {
233
                        "id" : ["SIMPLE_NAME", "to_integer"], "assoc_list" : [{
234
                          "actual_expr" : ["EXPRESSION", {
235
                            "args" : [["EXPRESSION", {
236
                              "args" : [["EXPRESSION", {
237
                                "args" : [["EXPRESSION", {
238
                                  "args" : [["CALL", ["FUNCTION_CALL", {
239
                                    "id" : ["SIMPLE_NAME", "unsigned"], "assoc_list" : [{
240
                                      "actual_designator" : ["SIMPLE_NAME", "V"]}
241
                                    ]}
242
                                  ]]]}
243
                                ]]}
244
                              ]]}
245
                            ]]}
246
                          ]}
247
                        ]}
248
                      ]]]}
249
                    ]]}
250
                  ]]}
251
                ]]}
252
              ]}
229 253
            ]]}
230 254
          ]}
231 255
        , {
......
237 261
                }
238 262
              ], "typeMark" : ["SIMPLE_NAME", "integer"], "isPure" : false}
239 263
            , "stmts" : [["RETURN_STATEMENT", {
240
              }
264
              "expr" : ["EXPRESSION", {
265
                "args" : [["EXPRESSION", {
266
                  "args" : [["EXPRESSION", {
267
                    "args" : [["EXPRESSION", {
268
                      "args" : [["CALL", ["FUNCTION_CALL", {
269
                        "id" : ["SIMPLE_NAME", "to_integer"], "assoc_list" : [{
270
                          "actual_expr" : ["EXPRESSION", {
271
                            "args" : [["EXPRESSION", {
272
                              "args" : [["EXPRESSION", {
273
                                "args" : [["EXPRESSION", {
274
                                  "args" : [["CALL", ["FUNCTION_CALL", {
275
                                    "id" : ["SIMPLE_NAME", "unsigned"], "assoc_list" : [{
276
                                      "actual_designator" : ["SIMPLE_NAME", "V"]}
277
                                    ]}
278
                                  ]]]}
279
                                ]]}
280
                              ]]}
281
                            ]]}
282
                          ]}
283
                        ]}
284
                      ]]]}
285
                    ]]}
286
                  ]]}
287
                ]]}
288
              ]}
241 289
            ]]}
242 290
          ]}
243 291
        ], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", {
vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/gna/bug040/huff_make_dhuff_tb_ac_huffsize.json
225 225
                ]]}
226 226
              ]}
227 227
            ], ["RETURN_STATEMENT", {
228
              }
228
              "expr" : ["EXPRESSION", {
229
                "args" : [["EXPRESSION", {
230
                  "args" : [["EXPRESSION", {
231
                    "args" : [["EXPRESSION", {
232
                      "args" : [["CALL", ["FUNCTION_CALL", {
233
                        "id" : ["SIMPLE_NAME", "to_integer"], "assoc_list" : [{
234
                          "actual_expr" : ["EXPRESSION", {
235
                            "args" : [["EXPRESSION", {
236
                              "args" : [["EXPRESSION", {
237
                                "args" : [["EXPRESSION", {
238
                                  "args" : [["CALL", ["FUNCTION_CALL", {
239
                                    "id" : ["SIMPLE_NAME", "unsigned"], "assoc_list" : [{
240
                                      "actual_designator" : ["SIMPLE_NAME", "V"]}
241
                                    ]}
242
                                  ]]]}
243
                                ]]}
244
                              ]]}
245
                            ]]}
246
                          ]}
247
                        ]}
248
                      ]]]}
249
                    ]]}
250
                  ]]}
251
                ]]}
252
              ]}
229 253
            ]]}
230 254
          ]}
231 255
        , {
......
237 261
                }
238 262
              ], "typeMark" : ["SIMPLE_NAME", "integer"], "isPure" : false}
239 263
            , "stmts" : [["RETURN_STATEMENT", {
240
              }
264
              "expr" : ["EXPRESSION", {
265
                "args" : [["EXPRESSION", {
266
                  "args" : [["EXPRESSION", {
267
                    "args" : [["EXPRESSION", {
268
                      "args" : [["CALL", ["FUNCTION_CALL", {
269
                        "id" : ["SIMPLE_NAME", "to_integer"], "assoc_list" : [{
270
                          "actual_expr" : ["EXPRESSION", {
271
                            "args" : [["EXPRESSION", {
272
                              "args" : [["EXPRESSION", {
273
                                "args" : [["EXPRESSION", {
274
                                  "args" : [["CALL", ["FUNCTION_CALL", {
275
                                    "id" : ["SIMPLE_NAME", "unsigned"], "assoc_list" : [{
276
                                      "actual_designator" : ["SIMPLE_NAME", "V"]}
277
                                    ]}
278
                                  ]]]}
279
                                ]]}
280
                              ]]}
281
                            ]]}
282
                          ]}
283
                        ]}
284
                      ]]]}
285
                    ]]}
286
                  ]]}
287
                ]]}
288
              ]}
241 289
            ]]}
242 290
          ]}
243 291
        ], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", {
vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/gna/bug040/huff_make_dhuff_tb_dc_huffcode.json
225 225
                ]]}
226 226
              ]}
227 227
            ], ["RETURN_STATEMENT", {
228
              }
228
              "expr" : ["EXPRESSION", {
229
                "args" : [["EXPRESSION", {
230
                  "args" : [["EXPRESSION", {
231
                    "args" : [["EXPRESSION", {
232
                      "args" : [["CALL", ["FUNCTION_CALL", {
233
                        "id" : ["SIMPLE_NAME", "to_integer"], "assoc_list" : [{
234
                          "actual_expr" : ["EXPRESSION", {
235
                            "args" : [["EXPRESSION", {
236
                              "args" : [["EXPRESSION", {
237
                                "args" : [["EXPRESSION", {
238
                                  "args" : [["CALL", ["FUNCTION_CALL", {
239
                                    "id" : ["SIMPLE_NAME", "unsigned"], "assoc_list" : [{
240
                                      "actual_designator" : ["SIMPLE_NAME", "V"]}
241
                                    ]}
242
                                  ]]]}
243
                                ]]}
244
                              ]]}
245
                            ]]}
246
                          ]}
247
                        ]}
248
                      ]]]}
249
                    ]]}
250
                  ]]}
251
                ]]}
252
              ]}
229 253
            ]]}
230 254
          ]}
231 255
        , {
......
237 261
                }
238 262
              ], "typeMark" : ["SIMPLE_NAME", "integer"], "isPure" : false}
239 263
            , "stmts" : [["RETURN_STATEMENT", {
240
              }
264
              "expr" : ["EXPRESSION", {
265
                "args" : [["EXPRESSION", {
266
                  "args" : [["EXPRESSION", {
267
                    "args" : [["EXPRESSION", {
268
                      "args" : [["CALL", ["FUNCTION_CALL", {
269
                        "id" : ["SIMPLE_NAME", "to_integer"], "assoc_list" : [{
270
                          "actual_expr" : ["EXPRESSION", {
271
                            "args" : [["EXPRESSION", {
272
                              "args" : [["EXPRESSION", {
273
                                "args" : [["EXPRESSION", {
274
                                  "args" : [["CALL", ["FUNCTION_CALL", {
275
                                    "id" : ["SIMPLE_NAME", "unsigned"], "assoc_list" : [{
276
                                      "actual_designator" : ["SIMPLE_NAME", "V"]}
277
                                    ]}
278
                                  ]]]}
279
                                ]]}
280
                              ]]}
281
                            ]]}
282
                          ]}
283
                        ]}
284
                      ]]]}
285
                    ]]}
286
                  ]]}
287
                ]]}
288
              ]}
241 289
            ]]}
242 290
          ]}
243 291
        ], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", {
vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/gna/bug040/huff_make_dhuff_tb_dc_huffsize.json
225 225
                ]]}
226 226
              ]}
227 227
            ], ["RETURN_STATEMENT", {
228
              }
228
              "expr" : ["EXPRESSION", {
229
                "args" : [["EXPRESSION", {
230
                  "args" : [["EXPRESSION", {
231
                    "args" : [["EXPRESSION", {
232
                      "args" : [["CALL", ["FUNCTION_CALL", {
233
                        "id" : ["SIMPLE_NAME", "to_integer"], "assoc_list" : [{
234
                          "actual_expr" : ["EXPRESSION", {
235
                            "args" : [["EXPRESSION", {
236
                              "args" : [["EXPRESSION", {
237
                                "args" : [["EXPRESSION", {
238
                                  "args" : [["CALL", ["FUNCTION_CALL", {
239
                                    "id" : ["SIMPLE_NAME", "unsigned"], "assoc_list" : [{
240
                                      "actual_designator" : ["SIMPLE_NAME", "V"]}
241
                                    ]}
242
                                  ]]]}
243
                                ]]}
244
                              ]]}
245
                            ]]}
246
                          ]}
247
                        ]}
248
                      ]]]}
249
                    ]]}
250
                  ]]}
251
                ]]}
252
              ]}
229 253
            ]]}
230 254
          ]}
231 255
        , {
......
237 261
                }
238 262
              ], "typeMark" : ["SIMPLE_NAME", "integer"], "isPure" : false}
239 263
            , "stmts" : [["RETURN_STATEMENT", {
240
              }
264
              "expr" : ["EXPRESSION", {
265
                "args" : [["EXPRESSION", {
266
                  "args" : [["EXPRESSION", {
267
                    "args" : [["EXPRESSION", {
268
                      "args" : [["CALL", ["FUNCTION_CALL", {
269
                        "id" : ["SIMPLE_NAME", "to_integer"], "assoc_list" : [{
270
                          "actual_expr" : ["EXPRESSION", {
271
                            "args" : [["EXPRESSION", {
272
                              "args" : [["EXPRESSION", {
273
                                "args" : [["EXPRESSION", {
274
                                  "args" : [["CALL", ["FUNCTION_CALL", {
275
                                    "id" : ["SIMPLE_NAME", "unsigned"], "assoc_list" : [{
276
                                      "actual_designator" : ["SIMPLE_NAME", "V"]}
277
                                    ]}
278
                                  ]]]}
279
                                ]]}
280
                              ]]}
281
                            ]]}
282
                          ]}
283
                        ]}
284
                      ]]]}
285
                    ]]}
286
                  ]]}
287
                ]]}
288
              ]}
241 289
            ]]}
242 290
          ]}
243 291
        ], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", {
vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/gna/bug040/huffbuff.json
225 225
                ]]}
226 226
              ]}
227 227
            ], ["RETURN_STATEMENT", {
228
              }
228
              "expr" : ["EXPRESSION", {
229
                "args" : [["EXPRESSION", {
230
                  "args" : [["EXPRESSION", {
231
                    "args" : [["EXPRESSION", {
232
                      "args" : [["CALL", ["FUNCTION_CALL", {
233
                        "id" : ["SIMPLE_NAME", "to_integer"], "assoc_list" : [{
234
                          "actual_expr" : ["EXPRESSION", {
235
                            "args" : [["EXPRESSION", {
236
                              "args" : [["EXPRESSION", {
237
                                "args" : [["EXPRESSION", {
238
                                  "args" : [["CALL", ["FUNCTION_CALL", {
239
                                    "id" : ["SIMPLE_NAME", "unsigned"], "assoc_list" : [{
240
                                      "actual_designator" : ["SIMPLE_NAME", "V"]}
241
                                    ]}
242
                                  ]]]}
243
                                ]]}
244
                              ]]}
245
                            ]]}
246
                          ]}
247
                        ]}
248
                      ]]]}
249
                    ]]}
250
                  ]]}
251
                ]]}
252
              ]}
229 253
            ]]}
230 254
          ]}
231 255
        , {
......
237 261
                }
238 262
              ], "typeMark" : ["SIMPLE_NAME", "integer"], "isPure" : false}
239 263
            , "stmts" : [["RETURN_STATEMENT", {
240
              }
264
              "expr" : ["EXPRESSION", {
265
                "args" : [["EXPRESSION", {
266
                  "args" : [["EXPRESSION", {
267
                    "args" : [["EXPRESSION", {
268
                      "args" : [["CALL", ["FUNCTION_CALL", {
269
                        "id" : ["SIMPLE_NAME", "to_integer"], "assoc_list" : [{
270
                          "actual_expr" : ["EXPRESSION", {
271
                            "args" : [["EXPRESSION", {
272
                              "args" : [["EXPRESSION", {
273
                                "args" : [["EXPRESSION", {
274
                                  "args" : [["CALL", ["FUNCTION_CALL", {
275
                                    "id" : ["SIMPLE_NAME", "unsigned"], "assoc_list" : [{
276
                                      "actual_designator" : ["SIMPLE_NAME", "V"]}
277
                                    ]}
278
                                  ]]]}
279
                                ]]}
280
                              ]]}
281
                            ]]}
282
                          ]}
283
                        ]}
284
                      ]]]}
285
                    ]]}
286
                  ]]}
287
                ]]}
288
              ]}
241 289
            ]]}
242 290
          ]}
243 291
        ], "ARCHITECTURE_STATEMENT_PART" : [["PROCESS_STATEMENT", {
vhdl_json/vhdl_files/2-exportOK/ghdl/ghdl/testsuite/gna/bug040/idctbuff.json
305 305
                ]]}
306 306
              ]}
307 307
            ], ["RETURN_STATEMENT", {
308
              }
308
              "expr" : ["EXPRESSION", {
309
                "args" : [["EXPRESSION", {
310
                  "args" : [["EXPRESSION", {
311
                    "args" : [["EXPRESSION", {
312
                      "args" : [["CALL", ["FUNCTION_CALL", {
313
                        "id" : ["SIMPLE_NAME", "to_integer"], "assoc_list" : [{
314
                          "actual_expr" : ["EXPRESSION", {
315
                            "args" : [["EXPRESSION", {
316
                              "args" : [["EXPRESSION", {
317
                                "args" : [["EXPRESSION", {
318
                                  "args" : [["CALL", ["FUNCTION_CALL", {
319
                                    "id" : ["SIMPLE_NAME", "unsigned"], "assoc_list" : [{
320
                                      "actual_designator" : ["SIMPLE_NAME", "V"]}
321
                                    ]}
322
                                  ]]]}
323
                                ]]}
324
                              ]]}
325
                            ]]}
326
                          ]}
327
                        ]}
328
                      ]]]}
329
                    ]]}
330
                  ]]}
331
                ]]}
332
              ]}
309 333
            ]]}
310 334
          ]}
311 335
        , {
......
317 341
                }
318 342
              ], "typeMark" : ["SIMPLE_NAME", "integer"], "isPure" : false}
319 343
            , "stmts" : [["RETURN_STATEMENT", {
320
              }
344
              "expr" : ["EXPRESSION", {
345
                "args" : [["EXPRESSION", {
346
                  "args" : [["EXPRESSION", {
347
                    "args" : [["EXPRESSION", {
348
                      "args" : [["CALL", ["FUNCTION_CALL", {
349
                        "id" : ["SIMPLE_NAME", "to_integer"], "assoc_list" : [{
350
                          "actual_expr" : ["EXPRESSION", {
351
                            "args" : [["EXPRESSION", {
352
                              "args" : [["EXPRESSION", {
353
                                "args" : [["EXPRESSION", {
354
                                  "args" : [["CALL", ["FUNCTION_CALL", {
355
                                    "id" : ["SIMPLE_NAME", "unsigned"], "assoc_list" : [{
356
                                      "actual_designator" : ["SIMPLE_NAME", "V"]}
357
                                    ]}
358
                                  ]]]}
359
                                ]]}
360
                              ]]}
361
                            ]]}
362
                          ]}
363
                        ]}
364
                      ]]]}
365
                    ]]}
366
                  ]]}
367
                ]]}
368
              ]}
321 369
            ]]}
322 370
          ]}
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