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1 2051e520 Arnaud Dieumegard
library ieee;
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use ieee.std_logic_1164.all;
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library ieee;
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use ieee.numeric_std.all;
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entity quant26bt_neg is
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	port (
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		clk : in  std_logic;
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		ra0_data : out std_logic_vector(31 downto 0);
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		ra0_addr : in  std_logic_vector(4 downto 0)
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	);
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end quant26bt_neg;
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architecture augh of quant26bt_neg is
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	-- Embedded RAM
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	type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
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	signal ram : ram_type := ("00000000000000000000000000111111", "00000000000000000000000000111110", "00000000000000000000000000011111", "00000000000000000000000000011110", "00000000000000000000000000011101", "00000000000000000000000000011100", "00000000000000000000000000011011", "00000000000000000000000000011010", "00000000000000000000000000011001", "00000000000000000000000000011000", "00000000000000000000000000010111", "00000000000000000000000000010110", "00000000000000000000000000010101", "00000000000000000000000000010100", "00000000000000000000000000010011", "00000000000000000000000000010010", "00000000000000000000000000010001", "00000000000000000000000000010000", "00000000000000000000000000001111", "00000000000000000000000000001110", "00000000000000000000000000001101", "00000000000000000000000000001100", "00000000000000000000000000001011", "00000000000000000000000000001010", "00000000000000000000000000001001", "00000000000000000000000000001000", "00000000000000000000000000000111", "00000000000000000000000000000110", "00000000000000000000000000000101", "00000000000000000000000000000100", "00000000000000000000000000000100", "00000000000000000000000000000000");
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	-- Little utility functions to make VHDL syntactically correct
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	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
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	--   This happens when accessing arrays with <= 2 cells, for example.
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	function to_integer(B: std_logic) return integer is
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		variable V: std_logic_vector(0 to 0);
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	begin
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		V(0) := B;
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		return to_integer(unsigned(V));
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	end;
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	function to_integer(V: std_logic_vector) return integer is
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	begin
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		return to_integer(unsigned(V));
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	end;
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begin
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	-- The component is a ROM.
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	-- There is no Write side.
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	-- The Read side (the outputs)
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	ra0_data <= ram( to_integer(ra0_addr) );
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end architecture;