Project

General

Profile

Download (1.33 KB) Statistics
| Branch: | Tag: | Revision:
1 2051e520 Arnaud Dieumegard
library ieee;
2
use ieee.std_logic_1164.all;
3
4
5
library ieee;
6
use ieee.numeric_std.all;
7
8
entity w_split3 is
9
	port (
10
		clk : in  std_logic;
11
		ra0_data : out std_logic_vector(7 downto 0);
12
		wa0_data : in  std_logic_vector(7 downto 0);
13
		wa0_addr : in  std_logic;
14
		wa0_en : in  std_logic;
15
		ra0_addr : in  std_logic
16
	);
17
end w_split3;
18
architecture augh of w_split3 is
19
20
	-- Embedded RAM
21
22
	type ram_type is array (0 to 1) of std_logic_vector(7 downto 0);
23
	signal ram : ram_type := (
24
		"00000111", "00000000"
25
	);
26
27
28
	-- Little utility functions to make VHDL syntactically correct
29
	--   with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
30
	--   This happens when accessing arrays with <= 2 cells, for example.
31
32
	function to_integer(B: std_logic) return integer is
33
		variable V: std_logic_vector(0 to 0);
34
	begin
35
		V(0) := B;
36
		return to_integer(unsigned(V));
37
	end;
38
39
	function to_integer(V: std_logic_vector) return integer is
40
	begin
41
		return to_integer(unsigned(V));
42
	end;
43
44
begin
45
46
	-- Sequential process
47
	-- It handles the Writes
48
49
	process (clk)
50
	begin
51
		if rising_edge(clk) then
52
53
			-- Write to the RAM
54
			-- Note: there should be only one port.
55
56
			if wa0_en = '1' then
57
				ram( to_integer(wa0_addr) ) <= wa0_data;
58
			end if;
59
60
		end if;
61
	end process;
62
63
	-- The Read side (the outputs)
64
65
	ra0_data <= ram( to_integer(ra0_addr) );
66
67
end architecture;