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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1787.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity c09s06b00x00p04n05i01787ent_a is
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  generic (
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    g0  :   Boolean        ;
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    g1  :   Bit            ;
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    g2  :   Character      ;
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    g3  :   SEVERITY_LEVEL ;
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    g4  :   Integer        ;
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    g5  :   Real           ;
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    g6  :   TIME           ;
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    g7  :   Natural        ;
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    g8  :   Positive       ;
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    g9  :   String         ;
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    gA  :   Bit_vector
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    );
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  port    (
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    port0  : out  Boolean        ;
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    port1  : out  Bit            ;
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    port2  : out  Character      ;
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    port3  : out  SEVERITY_LEVEL ;
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    port4  : out  Integer        ;
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    port5  : out  Real           ;
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    port6  : out  TIME           ;
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    port7  : out  Natural        ;
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    port8  : out  Positive       ;
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    port9  : out  String         ;
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    portA  : out  Bit_vector
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    );
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end c09s06b00x00p04n05i01787ent_a;
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architecture c09s06b00x00p04n05i01787arch_a of c09s06b00x00p04n05i01787ent_a is
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begin
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  port0 <= g0 after 11 ns;
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  port1 <= g1 after 11 ns;
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  port2 <= g2 after 11 ns;
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  port3 <= g3 after 11 ns;
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  port4 <= g4 after 11 ns;
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  port5 <= g5 after 11 ns;
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  port6 <= g6 after 11 ns;
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  port7 <= g7 after 11 ns;
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  port8 <= g8 after 11 ns;
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  port9 <= g9 after 11 ns;
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  portA <= gA after 11 ns;
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end c09s06b00x00p04n05i01787arch_a;
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ENTITY c09s06b00x00p04n05i01787ent IS
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END c09s06b00x00p04n05i01787ent;
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ARCHITECTURE c09s06b00x00p04n05i01787arch OF c09s06b00x00p04n05i01787ent IS
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  component MultiType
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    generic (
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      g0  :   Boolean        ;
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      g1  :   Bit            ;
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      g2  :   Character      ;
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      g3  :   SEVERITY_LEVEL ;
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      g4  :   Integer        ;
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      g5  :   Real           ;
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      g6  :   TIME           ;
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      g7  :   Natural        ;
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      g8  :   Positive       ;
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      g9  :   String         ;
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      gA  :   Bit_vector
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      );
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    port    (
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      port0  : out  Boolean        ;
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      port1  : out  Bit            ;
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      port2  : out  Character      ;
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      port3  : out  SEVERITY_LEVEL ;
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      port4  : out  Integer        ;
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      port5  : out  Real           ;
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      port6  : out  TIME           ;
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      port7  : out  Natural        ;
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      port8  : out  Positive       ;
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      port9  : out  String         ;
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      portA  : out  Bit_vector
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      );
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  end component;
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  for u1 : MultiType use entity work.c09s06b00x00p04n05i01787ent_a(c09s06b00x00p04n05i01787arch_a);
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  subtype reg32    is Bit_vector ( 31 downto 0 );
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  subtype string16    is String ( 1 to 16 );
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  signal signal0  :   Boolean        ;
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  signal signal1  :   Bit            ;
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  signal signal2  :   Character      ;
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  signal signal3  :   SEVERITY_LEVEL ;
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  signal signal4  :   Integer        ;
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  signal signal5  :   Real           ;
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  signal signal6  :   TIME           ;
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  signal signal7  :   Natural        ;
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  signal signal8  :   Positive       ;
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  signal signal9  :   String16       ;
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  signal signalA  :   Reg32          ;
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BEGIN
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  u1 : MultiType
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    generic map (
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      True,
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      '0',
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      '@',
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      NOTE,
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      123456789,
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      987654321.5,
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      110 ns,
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      12312,
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      3423,
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      "16 characters OK",
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      B"0101_0010_1001_0101_0010_1010_0101_0100"
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      )
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    port map (
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      signal0  ,
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      signal1  ,
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      signal2  ,
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      signal3  ,
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      signal4  ,
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      signal5  ,
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      signal6  ,
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      signal7  ,
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      signal8  ,
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      signal9  ,
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      signalA
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      );
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  TESTING: PROCESS
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  BEGIN
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    wait on signal0,signal1,signal2,signal3,signal4,signal5,signal6,signal7,signal8;
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    assert NOT(   signal0 = True                  and 
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                  signal1 = '0'                   and    
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                  signal2 = '@'                  and 
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                  signal3 = NOTE                and 
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                  signal4 = 123456789          and 
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                  signal5 = 987654321.5          and 
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                  signal6 = 110 ns              and 
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                  signal7 = 12312              and 
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                  signal8 = 3423              and 
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                  signal9 = "16 characters OK"    and 
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                  signalA = B"01010010100101010010101001010100")
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      report "***PASSED TEST: c09s06b00x00p04n05i01787"
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      severity NOTE;
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    assert (   signal0 = True                  and 
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               signal1 = '0'                   and    
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               signal2 = '@'                  and 
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               signal3 = NOTE                and 
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               signal4 = 123456789          and 
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               signal5 = 987654321.5          and 
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               signal6 = 110 ns              and 
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               signal7 = 12312              and 
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               signal8 = 3423              and 
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               signal9 = "16 characters OK"    and 
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               signalA = B"01010010100101010010101001010100")
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      report "***FAILED TEST: c09s06b00x00p04n05i01787 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
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      severity ERROR;
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    wait;
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  END PROCESS TESTING;
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END c09s06b00x00p04n05i01787arch;
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