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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1785.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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Package c09s06b00x00p04n07i01785pkg is
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  type info is record
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                 field_1 : integer;
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                 field_2 : real;
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               end record;
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  type stuff is array (Integer range 1 to 2) of info;
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end c09s06b00x00p04n07i01785pkg;
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use work.c09s06b00x00p04n07i01785pkg.all;
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entity c09s06b00x00p04n07i01785ent_a is
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  port    (
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    port_0  : in Boolean        ;
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    port_1  : in Bit            ;
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    port_2  : in Character      ;
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    port_3  : in SEVERITY_LEVEL ;
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    port_4  : in Integer        ;
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    port_5  : in Real           ;
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    port_6  : in TIME           ;
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    port_7  : in Natural        ;
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    port_8  : in Positive       ;
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    port_9  : in String         ; 
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    port_A  : in Bit_vector     ;
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    port_B  : in stuff
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    );
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end c09s06b00x00p04n07i01785ent_a;
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use work.c09s06b00x00p04n07i01785pkg.all;
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architecture c09s06b00x00p04n07i01785arch_a of c09s06b00x00p04n07i01785ent_a is
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  -- Check that the data was passed...
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begin
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  TESTING: PROCESS(port_0,port_1,port_2,port_3,port_4,port_5,port_6,port_7,port_8)
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  BEGIN
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    assert NOT(   port_0 = True                and 
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                  port_1 = '0'                and 
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                  port_2 = '@'                  and 
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                  port_3 = NOTE                and 
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                  port_4 = 123456789                 and
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                  port_5 = 987654321.5              and
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                  port_6 = 110 ns                  and
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                  port_7 = 12312                  and 
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                  port_8 = 3423                  and 
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                  port_9 = "16 characters OK"          and 
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                  port_A = B"01010010100101010010101001010100"    and 
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                  port_B = ((123, 456.7), (890, 135.7))) 
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      report "***PASSED TEST: c09s06b00x00p04n07i01785"
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      severity NOTE;
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    assert (   port_0 = True                and 
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               port_1 = '0'                and 
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               port_2 = '@'                  and 
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               port_3 = NOTE                and 
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               port_4 = 123456789                 and
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               port_5 = 987654321.5              and
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               port_6 = 110 ns                  and
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               port_7 = 12312                  and 
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               port_8 = 3423                  and 
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               port_9 = "16 characters OK"          and 
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               port_A = B"01010010100101010010101001010100"    and 
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               port_B = ((123, 456.7), (890, 135.7))) 
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      report "***FAILED TEST: c09s06b00x00p04n07i01785 - Port map aspect associates a single actual with each local port in the corresponding component declaration test failed."
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      severity ERROR;
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  END PROCESS TESTING;
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end c09s06b00x00p04n07i01785arch_a;
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-----------------------------------------------------------------------
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ENTITY c09s06b00x00p04n07i01785ent IS
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END c09s06b00x00p04n07i01785ent;
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use work.c09s06b00x00p04n07i01785pkg.all;
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ARCHITECTURE c09s06b00x00p04n07i01785arch OF c09s06b00x00p04n07i01785ent IS
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  subtype reg32    is Bit_vector ( 31 downto 0 );
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  subtype string16    is String ( 1 to 16 );
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  signal sig_0  :   Boolean        := TRUE;
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  signal sig_1  :   Bit            := '0';
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  signal sig_2  :   Character      := '@';
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  signal sig_3  :   SEVERITY_LEVEL := NOTE;
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  signal sig_4  :   Integer        := 123456789;
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  signal sig_5  :   Real           := 987654321.5;
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  signal sig_6  :   TIME           := 110 NS;
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  signal sig_7  :   Natural        := 12312;
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  signal sig_8  :   Positive       := 3423;
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  signal sig_9  :   String16       := "16 characters OK";
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  signal sig_A  :   REG32          := B"0101_0010_1001_0101_0010_1010_0101_0100";
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  signal sig_B  :   stuff          := (( 123, 456.7 ), ( 890, 135.7 ));
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  component MultiType
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    port    (
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      port_0  : in Boolean        ;
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      port_1  : in Bit            ;
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      port_2  : in Character      ;
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      port_3  : in SEVERITY_LEVEL ;
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      port_4  : in Integer        ;
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      port_5  : in Real           ;
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      port_6  : in TIME           ;
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      port_7  : in Natural        ;
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      port_8  : in Positive       ;
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      port_9  : in String         ;
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      port_A  : in Bit_vector     ;
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      port_B  : in stuff
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      );
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  end component;
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  for u1 : MultiType use entity work.c09s06b00x00p04n07i01785ent_a (c09s06b00x00p04n07i01785arch_a);
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BEGIN
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  u1 : MultiType
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    port map (
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      port_0 => sig_0,
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      port_1 => sig_1,
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      port_2 => sig_2,
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      port_3 => sig_3,
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      port_4 => sig_4,
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      port_5 => sig_5,
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      port_6 => sig_6,
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      port_7 => sig_7,
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      port_8 => sig_8,
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      port_9 => sig_9,
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      port_A => sig_A,
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      port_B => sig_B
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      );
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END c09s06b00x00p04n07i01785arch;
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