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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1748.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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ENTITY c09s05b00x00p16n01i01748ent IS
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END c09s05b00x00p16n01i01748ent;
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ARCHITECTURE c09s05b00x00p16n01i01748arch OF c09s05b00x00p16n01i01748ent IS
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  signal gate_1    : BIT;
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  signal gate_2    : BIT;
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  signal data_in    : BIT;
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  signal data_pass    : BIT;
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  signal data_latch    : BIT;
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BEGIN
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  gate_1    <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns;
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  gate_2    <= gate_1 after 1 ns;
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  data_in    <=    '1' after  5 ns, '0' after 25 ns,
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                   '1' after 35 ns, '0' after 36 ns,
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                   '1' after 37 ns, '0' after 38 ns,
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                   '1' after 39 ns, '0' after 40 ns,
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                   '1' after 41 ns, '0' after 42 ns;
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  B: block ((gate_1 and gate_2) = '1')
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  begin
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    data_pass    <=       data_in;
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    data_latch    <= guarded    data_in;
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  end block;
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  TESTING: PROCESS(data_pass,data_latch)
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    variable ok : integer := 1;
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  BEGIN
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    if (now = 5 ns) then
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      if not(data_pass'event and data_pass = '1' and data_latch'quiet and data_latch = '0') then
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        ok := 0;
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      end if;
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    elsif (now = 11 ns) then
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      if not(data_latch'event and data_latch = '1' and data_pass'quiet and data_pass = '1') then
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        ok := 0;
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      end if;
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    elsif (now = 25 ns) then
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      if not(data_latch'quiet and data_latch = '1' and data_pass'event and data_pass = '0') then
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        ok := 0;
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      end if;
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    elsif (now = 31 ns) then
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      if not(data_latch'event and data_latch = '0' and data_pass'quiet and data_pass = '0') then
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        ok := 0;
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      end if;
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    elsif (now = 35 ns) then
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      if not(data_latch'event and data_latch = '1' and data_pass'event and data_pass = '1') then
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        ok := 0;
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      end if;
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    elsif (now = 36 ns) then
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      if not(data_latch'event and data_latch = '0' and data_pass'event and data_pass = '0') then
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        ok := 0;
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      end if;
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    elsif (now = 37 ns) then
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      if not(data_latch'event and data_latch = '1' and data_pass'event and data_pass = '1') then
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        ok := 0;
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      end if;
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    elsif (now = 38 ns) then
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      if not(data_latch'event and data_latch = '0' and data_pass'event and data_pass = '0') then
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        ok := 0;
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      end if;
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    elsif (now = 39 ns) then
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      if not(data_latch'event and data_latch = '1' and data_pass'event and data_pass = '1') then
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        ok := 0;
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      end if;
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    elsif (now = 40 ns) then
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      if not(data_latch'quiet and data_latch = '1' and data_pass'event and data_pass = '0') then
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        ok := 0;
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      end if;
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    elsif (now = 41 ns) then
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      if not(data_latch'quiet and data_latch = '1' and data_pass'event and data_pass = '1') then
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        ok := 0;
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      end if;
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    end if;
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    if (now > 41 ns) then   
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      assert NOT( ok=1 )
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        report "***PASSED TEST: c09s05b00x00p16n01i01748"
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        severity NOTE;
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      assert ( ok=1 )
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        report "***FAILED TEST: c09s05b00x00p16n01i01748 - Concurrent signal assignment test failed."
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        severity ERROR;
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    end if;
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  END PROCESS TESTING;
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END c09s05b00x00p16n01i01748arch;
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