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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1747.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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ENTITY c09s05b00x00p12n02i01747ent IS
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  function resolve_bit ( inputs : bit_vector) return bit is
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    VARIABLE val : bit := '0';
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  begin
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    if inputs'length = 0 then
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      return val;
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    else
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      for i in inputs'range LOOP
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        if inputs(i) = '1' then return '1'; end if;
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      END LOOP;
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      return '0';
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    end if;
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  end resolve_bit;
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END c09s05b00x00p12n02i01747ent;
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ARCHITECTURE c09s05b00x00p12n02i01747arch OF c09s05b00x00p12n02i01747ent IS
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  signal      a      : resolve_bit bit BUS;
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  signal    b      : resolve_bit bit BUS;
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  signal    grd    : boolean;
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BEGIN
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  grd <=    TRUE    after 10 ns,
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            FALSE   after 20 ns; 
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  block_label : BLOCK (grd)
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  begin
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    b <= guarded '1' after 1 ns;
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  end block block_label;
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  block_label_1 : BLOCK (grd)
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  begin
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    TESTING: PROCESS
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    BEGIN
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      if GUARD then
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        a <= '1' after 1 ns;
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      else
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        a <= NULL;
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      end if;
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      wait on GUARD, a;
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    END PROCESS TESTING;
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  end block block_label_1;
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  process(a,b)
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    variable f1, f2 : integer := 0;
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  begin
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    if    (now = 11 ns) and (a=b) then
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      f1 := 1;
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    end if;
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    if    (now = 20 ns) and (a=b) then
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      f2 := 1;
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    end if;
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    if (now = 20 ns) then   
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      assert NOT((f1=1) and (f2=1)) 
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        report "***PASSED TEST: c09s05b00x00p12n02i01747"
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        severity NOTE;
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      assert ((f1=1) and (f2=1)) 
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        report "***FAILED TEST: c09s05b00x00p12n02i01747 - The concurrent guarded signal assignment statement has an equivalent process statement."
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        severity ERROR;
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    end if;
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  end process;
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END c09s05b00x00p12n02i01747arch;
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