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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1655.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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package c09s00b00x00p05n01i01655pkg is
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  procedure cpc (constant loc : string);
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end c09s00b00x00p05n01i01655pkg;
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package body c09s00b00x00p05n01i01655pkg is
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  procedure cpc (constant loc : string) is      -- concurrent procedure
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  begin
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    assert false
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      report "Concurrent procedure called from " & loc            
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      severity note ;
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  end cpc;
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end c09s00b00x00p05n01i01655pkg;
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use work.c09s00b00x00p05n01i01655pkg.all;
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entity c09s00b00x00p05n01i01655ent_a is
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  port (signal pi : in  bit;
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        signal po : out bit
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        );
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begin
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  cas : assert false
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    report "Labeled concurrent assert called from component."
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    severity note ;
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  cpcc : cpc("component entity");
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  ppsc :                                -- passive process stmt
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  process (pi)
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  begin
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    assert false
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      report "Passive process can be labeled in component."
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      severity note ;
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  end process;
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end c09s00b00x00p05n01i01655ent_a;
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architecture c09s00b00x00p05n01i01655arch_a of c09s00b00x00p05n01i01655ent_a is
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begin
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  cpc("component architecture");
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end;
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use work.c09s00b00x00p05n01i01655pkg.all, work.c09s00b00x00p05n01i01655ent_a;
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ENTITY c09s00b00x00p05n01i01655ent IS
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  port (signal pi : in  bit;
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        signal po : out bit
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        );
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begin
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  cas : assert false
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    report "Labeled concurrent assert called from entity."
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    severity note ;
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  cpce : cpc("entity.");
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  ppse :                                -- passive process stmt
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  process (pi)
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  begin
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    assert false
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      report "Passive process can be labeled in entity."
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      severity note ;
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  end process;
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END c09s00b00x00p05n01i01655ent;
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ARCHITECTURE c09s00b00x00p05n01i01655arch OF c09s00b00x00p05n01i01655ent IS
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  signal lab_sig : boolean := true;
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  component comp
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    port (signal pi : in bit;
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          signal po : out bit
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          );
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  end component; -- comp
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  for lcia : comp use entity work.c09s00b00x00p05n01i01655ent_a(c09s00b00x00p05n01i01655arch_a)
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    port map (pi, po);
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BEGIN
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  casa : assert false
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    report "Labeled concurrent assert called from architecture."
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    severity note ;
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  cpca : cpc("architecture.");
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  ppsa : process (pi)
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  begin
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    assert false
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      report "Passive process can be labeled in architecture."
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      severity note ;
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  end process;
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  lba: block
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  begin
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    cpcb : cpc("block.");
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    casb : assert false
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      report "Labeled concurrent assert called from labeled block."
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      severity note ;
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  end block lba;
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  csa : lab_sig <= false;
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  assert lab_sig
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    report "Labeled concurrent signal assignment executed in architecture."
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    severity note ;
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  lcia : comp
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    port map (pi => pi, po => po);
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  TESTING: PROCESS
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  BEGIN
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    assert FALSE 
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      report "***PASSED TEST: c09s00b00x00p05n01i01655 - This test need manual check to the ASSERTION statement."
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      severity NOTE;
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    wait;
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  END PROCESS TESTING;
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END c09s00b00x00p05n01i01655arch;
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