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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1653.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity c09s00b00x00p02n01i01653ent_a is
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  port (signal ss : in integer);
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end c09s00b00x00p02n01i01653ent_a;
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architecture c09s00b00x00p02n01i01653arch_a of c09s00b00x00p02n01i01653ent_a is
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begin
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  process
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  begin
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    wait;
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  end process;
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end c09s00b00x00p02n01i01653arch_a;
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ENTITY c09s00b00x00p02n01i01653ent IS
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  port ( Pt    : in BOOLEAN;
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         PTO    : out BIT) ;
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END c09s00b00x00p02n01i01653ent;
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ARCHITECTURE c09s00b00x00p02n01i01653arch OF c09s00b00x00p02n01i01653ent IS
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  component FO 
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    port (signal ss : in INTEGER);
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  end component ;
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  for Ls : FO use entity work.c09s00b00x00p02n01i01653ent_a(c09s00b00x00p02n01i01653arch_a);
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  signal S1, S2    : Integer;
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  signal S       : INTEGER;
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BEGIN
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  -- concurrent signal statement
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  S <= transport 5;
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  -- concurrent assertion statement
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  assert ( not PT)
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    report " dead wire "
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    severity WARNING;
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  -- generate
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  L_G_1:  for I in 1 to 1 generate
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    L_X_2:    block
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      signal S3 : Bit;
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    begin
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      S2 <= transport 1;
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    end block;
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  end generate;
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  -- component instatiation
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  Ls : FO port map (S1);
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  TESTING: PROCESS
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  BEGIN
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    assert FALSE 
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      report "***PASSED TEST: c09s00b00x00p02n01i01653" 
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      severity NOTE;
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    wait;
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  END PROCESS TESTING;
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END c09s00b00x00p02n01i01653arch;
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