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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc143.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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package c04s03b02x02p12n01i00143pkg is
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  type fourstate is ('0','1','x','z');
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  function fourstate_to_bit(x : fourstate) return bit;
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  procedure simple ( crude : in bit;
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                     signal refined : out bit);
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end c04s03b02x02p12n01i00143pkg;
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package body c04s03b02x02p12n01i00143pkg is
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  procedure simple ( crude : in bit;
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                     signal refined : out bit) is
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  begin
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    refined <= crude after 5 ns;
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  end simple;
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  function fourstate_to_bit(x : fourstate) return bit is
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    variable newval: bit := '0';
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  begin
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    case x is
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      when '0' => newval := '0';
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      when '1' => newval := '1';
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      when 'z' => newval := '0';
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      when 'x' => newval := '0';
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    end case;
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    return newval;
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  end fourstate_to_bit;
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end c04s03b02x02p12n01i00143pkg;
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use work.c04s03b02x02p12n01i00143pkg.all;
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ENTITY c04s03b02x02p12n01i00143ent IS
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  port( x, y: in fourstate);
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END c04s03b02x02p12n01i00143ent;
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ARCHITECTURE c04s03b02x02p12n01i00143arch OF c04s03b02x02p12n01i00143ent IS
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  signal yint : bit;
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BEGIN
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  simple ( fourstate_to_bit(y) , yint);
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  TESTING: PROCESS
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  BEGIN
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    wait for 10 ns;
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    assert NOT( yint = '0' )
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      report "***PASSED TEST: c04s03b02x02p12n01i00143"
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      severity NOTE;
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    assert ( yint = '0' )
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      report "***FAILED TEST: c04s03b02x02p12n01i00143 - Type conversion test failed."
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      severity ERROR;
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    wait;
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  END PROCESS TESTING;
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END c04s03b02x02p12n01i00143arch;
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