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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1316.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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ENTITY c08s04b00x00p07n04i01316ent IS
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END c08s04b00x00p07n04i01316ent;
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ARCHITECTURE c08s04b00x00p07n04i01316arch OF c08s04b00x00p07n04i01316ent IS
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  type sigrec is
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    record
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      B1 : bit;
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      B2 : integer;
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      B3 : boolean;
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    end record;
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  signal S1 : bit;
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  signal S2 : integer;
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  signal S3 : boolean;
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BEGIN
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  TESTING: PROCESS
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  BEGIN
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    (S1, S2, S3) <= sigrec'('0',2,false);
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    wait for 10 ns;
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    assert NOT( (S1 = '0') and (S2 = 2) and (S3 = false) )
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      report "***PASSED TEST: c08s04b00x00p07n04i01316"
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      severity NOTE;
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    assert ( (S1 = '0') and (S2 = 2) and (S3 = false) )
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      report "***FAILED TEST: c08s04b00x00p07n04i01316 - Right hand side values are assigned to the drivers associated with the signal named as the corresponding subelement of the aggreate."
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      severity ERROR;
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    wait;
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  END PROCESS TESTING;
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END c08s04b00x00p07n04i01316arch;
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