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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1205.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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package c08s01b00x00p08n03i01205pkg is
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  -- Type declarations.
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  type    SWITCH_LEVEL   is ( '0', '1', 'X' );
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  type    S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
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  -- Define the bus resolution function.
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  function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
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  -- Further type declarations.
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  subtype SWITCH_T       is switchF SWITCH_LEVEL;
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  type    WORD           is array(0 to 31) of SWITCH_T;
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end c08s01b00x00p08n03i01205pkg;
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package body c08s01b00x00p08n03i01205pkg is
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  function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
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  begin
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    return( S(1) );
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  end switchf;
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end c08s01b00x00p08n03i01205pkg;
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use work.c08s01b00x00p08n03i01205pkg.all;
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entity c08s01b00x00p08n03i01205ent_a is
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  generic ( GenOne : in INTEGER ; GenTwo :INTEGER);
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end c08s01b00x00p08n03i01205ent_a;
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-------------------------------------------------------------------------
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architecture c08s01b00x00p08n03i01205arch_a of c08s01b00x00p08n03i01205ent_a is
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  -- Type definitions.
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  type WORD2 is array( 0 to 31 ) of SWITCH_LEVEL;
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  -- Local signals.
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  signal A, B    : WORD;
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  signal UnResolved    : WORD2;
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begin
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  TEST_PROCESS:  process
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    -- Constant declarations.
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    constant One : INTEGER := 1;
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    constant Two : INTEGER := 2;
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    -- Local variables.
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    variable ShouldBeTime : TIME;
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    variable I            : INTEGER;
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    variable k    : integer := 0;
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  begin
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    -- Test locally static signals.
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    A( 1 ) <= 'X' after 10 ns;
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    A( 2 ) <= 'X' after 5 ns;
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    ShouldBeTime := NOW + 10 ns;
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    wait on A(1);
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    -- Should wake up when the A(1) assignment takes place.
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    assert (A(1) = 'X');
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    assert (ShouldBeTime = NOW);
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    if (A(1) /= 'X' and ShouldBeTime /= Now) then
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      k := 1;
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    end if;
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    -- Perform same test, but with a constant.
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    A( One ) <= '1' after 10 ns;
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    A( Two ) <= '1' after 5 ns;
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    ShouldBeTime := NOW + 10 ns;
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    wait on A(One);
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    -- Should wake up when the A(1) assignment takes place.
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    assert (A(One) = '1');
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    assert (ShouldBeTime = NOW);
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    if (A(One) /= '1' and ShouldBeTime /= Now) then
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      k := 1;
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    end if;
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    -- Perform same test, but with a generic.   (globally static)
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    A( GenOne ) <= 'X' after 10 ns;
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    A( GenTwo ) <= 'X' after 5 ns;
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    ShouldBeTime := NOW + 10 ns;
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    wait on A(GenOne);
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    -- Should wake up when the A(1) assignment takes place.
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    assert (A(GenOne) = 'X');
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    assert (ShouldBeTime = NOW);
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    if (A(GenOne) /= 'X' and ShouldBeTime /= Now) then
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      k := 1;
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    end if;
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    -- Perform same test, but assigning to the whole thing.
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    A <= ('1','1','1','1','1','1','1','1','1','1',
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          '1','1','1','1','1','1','1','1','1','1',
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          '1','1','1','1','1','1','1','1','1','1',
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          '1','1') after 10 ns;
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    ShouldBeTime := NOW + 10 ns;
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    wait on A(GenOne);
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    -- Should wake up when the all assignments take place.
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    assert (A(GenOne) = '1');
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    assert (ShouldBeTime = NOW);
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    if (A(GenOne) /= '1' and ShouldBeTime /= Now) then
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      k := 1;
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    end if;
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    -- Now, perform same test but assigning to a composite
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    -- signal which is NOT resolved at the scalar subelement
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    -- level.
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    UnResolved <= ('1','1','1','1','1','1','1','1','1','1',
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                   '1','1','1','1','1','1','1','1','1','1',
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                   '1','1','1','1','1','1','1','1','1','1',
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                   '1','1') after 10 ns;
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    ShouldBeTime := NOW + 10 ns;
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    wait on UnResolved(GenOne);
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    -- Should wake up when the all assignments take place.
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    assert (UnResolved(GenOne) = '1');
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    assert (ShouldBeTime = NOW);
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    if (UnResolved(GenOne) /= '1' and ShouldBeTime /= Now) then
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      k := 1;   
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    end if;
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    assert NOT(k = 0) 
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      report "***PASSED TEST: c08s01b00x00p08n03i01205" 
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      severity NOTE;
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    assert (k = 0) 
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      report "***FAILED TEST: c08s01b00x00p08n03i01205 - All statically indexed signal names (both locally and globally static) may be used in the sensitivity clause of a wait statement." 
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      severity ERROR;
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    wait;
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  end process TEST_PROCESS;
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end c08s01b00x00p08n03i01205arch_a;
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use work.c08s01b00x00p08n03i01205pkg.all;
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ENTITY c08s01b00x00p08n03i01205ent IS
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END c08s01b00x00p08n03i01205ent;
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ARCHITECTURE c08s01b00x00p08n03i01205arch OF c08s01b00x00p08n03i01205ent IS
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  component c08s01b00x00p08n03i01205ent_a
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    generic( GenOne : in INTEGER;  GenTwo : INTEGER );
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  end component;
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  for T1 : c08s01b00x00p08n03i01205ent_a use entity work.c08s01b00x00p08n03i01205ent_a(c08s01b00x00p08n03i01205arch_a); 
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BEGIN
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  T1 : c08s01b00x00p08n03i01205ent_a generic map ( 1, 2 );
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END c08s01b00x00p08n03i01205arch;
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