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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1091.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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package c06s05b00x00p02n01i01091pkg is
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  type FIVE    is range 1 to 5;
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  type ABASE    is array (FIVE range <>) of BOOLEAN;
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  subtype A1    is ABASE(FIVE);
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  attribute    AT1 : A1;
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  function    fat1(i:integer) return a1;
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end c06s05b00x00p02n01i01091pkg;
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package body c06s05b00x00p02n01i01091pkg is
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  function fat1(i:integer) return a1 is
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    variable va1 : a1;
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  begin
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    return Va1;
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  end fat1;
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end c06s05b00x00p02n01i01091pkg;
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use work.c06s05b00x00p02n01i01091pkg.all;
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ENTITY c06s05b00x00p02n01i01091ent IS
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  port (PT: BOOLEAN) ;
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  attribute AT1 of PT : signal is fat1(8);
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END c06s05b00x00p02n01i01091ent;
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ARCHITECTURE c06s05b00x00p02n01i01091arch OF c06s05b00x00p02n01i01091ent IS
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BEGIN
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  TESTING: PROCESS
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    variable V1 : A1;
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  BEGIN
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    V1(2 to 4) := PT'AT1(2 to 4);
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    assert NOT(V1(2 to 4)=(false,false,false))
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      report "***PASSED TEST: c06s05b00x00p02n01i01091"
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      severity NOTE;
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    assert (V1(2 to 4)=(false,false,false))
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      report "***FAILED TEST: c06s05b00x00p02n01i01091 - Slice name consists of a single discrete range enclosed within parentheses."
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      severity ERROR;
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    wait;
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  END PROCESS TESTING;
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END c06s05b00x00p02n01i01091arch;
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